Physical-Only Cells in VLSI: Tap, Endcap, Filler and Decap

Physical-only cells are the quiet majority of many placed designs: they do not appear as gates in the RTL, yet they decide whether you pass latch-up spacing, row-edge implant rules, site legality after placement, and dynamic IR on a hot clock domain. Four families dominate standard-cell physical design interviews and day-to-day PnR: well taps (substrate/well pick-ups), endcaps, fillers, and decaps. Get them wrong and you inherit DRC, LVS, reliability or voltage-noise failures that no timing ECO can paper over.

This post is a practitioner guide: what each cell type does, where the tool inserts it, how it interacts with floorplan and placement, illustrative spacing/ Cap examples (not foundry numbers), a debug flowchart, and interview Q&As. Related reading: Latch-up in CMOS, IR Drop Analysis in VLSI, Technology DRCs in VLSI, PODE vs CPODE, ECO in VLSI Physical Design, Electromigration in VLSI, Antenna Effect in VLSI, Routing Congestion in VLSI, Floorplan and Placement.

What “physical-only” means#

In a typical liberty / LEF flow, logical standard cells have pins that the netlist connects (D, Q, A, Y, CK, …). Physical-only (sometimes called physical cells, special cells, or filler/tap/endcap/decap as a group) usually expose only power/ground connectivity—or no signal pins at all. The placer and a dedicated insert physical cells step put them into the DEF so that:

1. Wells and substrate stay biased (taps).
2. Cell rows and hard-macro abutments satisfy edge / implant / diffusion-break rules (endcaps; related to diffusion-break strategy—see PODE vs CPODE).
3. Leftover sites after legalization are filled so OD/well patterns and density rules remain legal (fillers; density also ties to Technology DRCs).
4. Local decoupling capacitance sits next to switching logic (decaps; pairs with IR drop analysis).

They are not optional decoration. A design that “routes clean” but skips taps or endcaps fails sign-off DRC/LVS or reliability screens. Exact cell names (TAPX1, FILL2, DECAP64, ENDCAP, …) are library-specific—learn the roles, then map them to your PDK kit.

Well tap cells: bias, latch-up and spacing#

Why wells must be tied#

CMOS sits in N-wells (for PMOS) and P-substrate / P-wells (for NMOS). Those body regions must be held near the intended rail—typically N-well to VDD and P-sub/P-well to VSS—through tap (pick-up) structures: N+ diffusion in N-well tied to VDD, P+ in P-sub tied to VSS. If a well floats or the tap grid is too coarse, substrate current from I/O, ESD, or switching can forward-bias parasitic bipolars and trigger latch-up (parasitic SCR). Mechanism, triggers and JESD78-style testing are covered in Latch-up in CMOS; this post focuses on what the PD engineer places.

Placement rules you will actually use#

Foundries publish a maximum tap-to-device or tap-to-tap distance (and often separate rules for N-well vs substrate). The PnR tool’s tap-insertion engine (or a dedicated script) stamps tap cells on a grid that satisfies that pitch, plus keep-outs near sensitive analog, high-voltage, or I/O rings. Practical checklist:

Worked example A: tap pitch (illustrative)#

All numbers are invented for teaching—not a real DRC deck.

• Rule (illustrative): every point in an N-well must be within (30\,\mu\mathrm{m}) of an N-well tap.
• You place taps on a square grid of pitch (P). Worst-case distance to the nearest tap (grid centre) is ((P/2)\sqrt{2}).
• Require ((P/2)\sqrt{2} \le 30) → (P \le 30\sqrt{2} \approx 42.4\,\mu\mathrm{m}).
• A PD script that stamps taps every (40\,\mu\mathrm{m}) in X and Y would meet this cartoon rule with margin; every (50\,\mu\mathrm{m}) would not.

In silicon the rule is rarely a single Euclidean number—it may be Manhattan, layer-specific, or relaxed under deep N-well. Always read the tech deck, not a blog formula. Interview answer: explain the worst-case distance to nearest tap idea, then say you obey the foundry spacing and the tool’s tap report.

Common tap failures#

• Tap spacing DRC after dense filler/ECO: a late metal-only ECO swapped cells and opened a hole—re-insert taps before sign-off.
• Wrong power net: tap tied to the neighbour domain’s VDD in a multi-voltage floorplan.
• Blocked sites: hard macro, blockage, or reserved spare strip ate the legal tap site—extend the grid or move blockage.
• Assuming always-on fillers are taps: fillers do not replace well pick-ups unless the library explicitly combines the roles (rare; do not assume).

Endcap cells: closing the row#

Standard-cell rows are built from sites. At the left/right ends of a row—and wherever a row abuts a hard macro, voltage-area boundary, or diffusion break—the library often requires endcap (or boundary) cells. They terminate well, implant, and OD patterns so you do not leave an illegal “open” cell edge. Related abutment topics (single vs double diffusion break, PODE/CPODE cell edges) live in PODE vs CPODE.

Endcaps are physical-only: no logic function. Typical insertion points:

1. Automatic row termination during placement legalization / chip finishing.
2. Around macros and fence boundaries.
3. At power-domain / voltage-area edges when the methodology demands domain-aware boundary cells.

If you disable endcap insertion “to save area,” expect edge DRC and odd LVS/antenna interactions later. Area cost is usually tiny versus a respinned abutment fix.

Filler cells: site fill and pattern continuity#

After placement and legalization, unused sites remain between standard cells. Filler cells occupy those sites. Motivations:

1. Well / OD continuity — many nodes dislike long interruptions in diffusion or well stripes inside a row.
2. Density and CMP — empty sites can create local density holes that fail density DRCs or create manufacturing risk; fillers (and metal fill, a separate step) help.
3. Legalization hygiene — tools expect a fully occupied site map before tap/decap refinement and routing.
4. ECO landing pads — some flows leave intentional gaps or use spare cells; fillers occupy the rest so the row stays legal (ECO).

Fillers come in width variants (FILL1, FILL2, FILL4, …) so a bin-packing style fill can match leftover site counts. They generally do not provide intentional decoupling (that is the decap family’s job) and do not replace taps.

Worked example B: filling a gap (illustrative)#

A row has a (9)-site hole. Available fillers: 1-, 2-, and 4-site widths. One legal packing: (4+4+1). Another: (4+2+2+1). A broken packing that leaves a 3-site hole with no FILL3 in the library fails fill—hence libraries ship a rich width set, or the flow allows a no-fill exception only where the tech deck permits.

Filler vs spare vs decap#

Do not “fix” a reserved spare strip with unremovable fillers if your ECO plan needs those sites—coordinate with the ECO methodology.

Decap cells: fighting dynamic IR#

Decap (decoupling capacitor) cells place MOS capacitance between VDD and VSS (or between domain rails). When a bus or ALU switches, instantaneous current (I(t)) is drawn from the PDN. Series R and L on the grid turn that into voltage droop—dynamic IR—which slows cells and can create hold/setup surprises. Static IR (average current × resistance) is necessary but not sufficient; see IR Drop Analysis in VLSI.

Where to put decaps#

• Near high di/dt blocks (clock dense regions, wide datapaths, memory interfaces).
• Under or beside power straps with good via access (a decap with starved vias helps less).
• Balanced against area, leakage, and routing — large decap arrays eat placement util and can worsen congestion.
• Respect analog keep-outs and noise-sensitive IP; blind decap dumping next to a PLL can be worse than helpful.

Worked example C: charge estimate (illustrative)#

Teaching numbers only.

• A block draws an extra (\Delta I = 50\,\mathrm{mA}) for (\Delta t = 200\,\mathrm{ps}) during a simultaneous switch event.
• Charge needed ≈ (\Delta I \times \Delta t = 0.05 \times 2\times10^{-10} = 10\,\mathrm{pC}).
• If you allow only (\Delta V = 20\,\mathrm{mV}) of droop from local C, need (C \ge Q/\Delta V = 10\,\mathrm{pC}/0.02\,\mathrm{V} = 500\,\mathrm{pF}).
• If one library decap offers an illustrative (25\,\mathrm{fF}) of effective C, you would need on the order of (500\,\mathrm{pF}/25\,\mathrm{fF} = 20{,}000) such cells for that cartoon event alone—which is why real methodologies use a mix of package/board C, on-die grid C, intentional decap arrays, and activity management—not a single cell type. The interview point is the (C \ge Q/\Delta V) reasoning, not the invented fF.

Decap also has leakage and sometimes reliability limits (oxide stress). Follow the library’s max parallel guidance and the IR sign-off deck; never invent foundry capacitance tables in a blog or interview.

Decap and EM#

Heavy switching near thin straps can create EM risk on power vias and wires even if average IR looks fine. After major decap moves, re-check EM and dynamic IR together.

Where physical-only cells sit in the PD flow#

A typical order (names vary by tool):

1. Floorplan — voltage areas, macros, tap/decap budgets, spare planning (Floorplan).
2. Placement + legalization — standard cells on sites (Placement).
3. Tap insertion — satisfy well spacing.
4. Endcap insertion — close edges / abutment.
5. Filler fill — pack remaining sites (often iterative with decap).
6. Decap insertion / optimization — driven by IR or utilization targets.
7. CTS / route / chip finish — metal fill, antenna fixes (Antenna Effect), spare/ECO prep.
8. Sign-off — DRC (including tap spacing), LVS well ties, static+dynamic IR, EM.

Late ECOs that delete fillers or move logic must re-run the physical-cell steps that your methodology marks as mandatory before tapeout. A timing-only ECO mindset that ignores taps is a classic tapeout scare.

Interaction with multi-voltage, always-on and spares#

• Level shifters / isolation / retention are logical special cells (thin stubs exist on the site for some of these); they are not fillers. Physical-only cells still surround them and must use the correct rail for each voltage area.
• Always-on islands need taps and endcaps consistent with the always-on well/rail strategy.
• Spare cells reserved for ECO should be excluded from aggressive filler/decap overwrite unless the flow documents how to reclaim them.

Debug flowchart: DRC, latch-up spacing, or IR after place#

When physical-cell related failures show up late, walk the roles in order instead of random cell dumping.

Practical habits:

1. Read the exact DRC/LVS/IR message—tap spacing ≠ density ≠ endcap edge.
2. Diff DEF before/after the last ECO: did you delete a tap row?
3. Confirm voltage-area membership of failing taps/decaps.
4. For IR, prefer dynamic hotspots over blindly maxing decap util.
5. Re-legalize and re-fill after any site surgery; then purge stale reports.

Interview Q&As#

Q1. What are physical-only cells?
A. Cells with no (or negligible) logical netlist function—typically taps, endcaps, fillers and decaps—inserted so layout meets well bias, edge, site-fill and decoupling requirements.

Q2. Why do we need well taps?
A. To tie N-wells to VDD and P-substrate/P-wells to VSS so bodies do not float, reducing latch-up risk and satisfying well-tie DRCs/LVS.

Q3. What sets tap placement pitch?
A. Foundry maximum tap-to-device / tap-to-tap spacing (and related rules). Tools insert a grid that meets those constraints.

Q4. Endcap vs filler—what is the difference?
A. Endcaps terminate row/macro/domain edges for abutment and implant legality; fillers occupy leftover sites inside rows for continuity/density/legality.

Q5. Do fillers provide decoupling?
A. Generally no. Use dedicated decap cells when you need intentional C between rails.

Q6. How do decaps help IR drop?
A. They supply local charge during current spikes, reducing dynamic voltage droop on the PDN; verify with dynamic IR analysis.

Q7. Can you skip endcaps to save area?
A. Not if the tech deck requires them—edge DRCs will fail. Area savings are usually trivial versus the risk.

Q8. What happens to taps after a large ECO?
A. Spacing holes can open; re-run tap insertion/checks before sign-off.

Q9. Filler vs spare cell?
A. Fillers pack unused sites; spares are reserved logic for future metal ECOs and must remain available per methodology.

Q10. How do physical-only cells relate to PODE/CPODE?
A. Diffusion-break and cell-edge strategies affect what boundary/endcap styles the library provides; see PODE vs CPODE.

Q11. Multi-voltage design—any tap gotcha?
A. Taps must connect to the correct domain rails; a tap on the wrong VDD is a functional/reliability bug.

Q12. Decap insertion hurt my congestion—what now?
A. Reduce decap in cold regions, prefer locations under straps, balance vs IR targets, and fix floorplan/channel issues—see Routing Congestion.

FAQ#

Are tie-high / tie-low cells the same as taps?
No. Tie cells provide constant logical 1/0 to signal pins. Taps bias wells to power rails. Different problem.

Is metal fill a physical-only “cell”?
Metal fill is usually a routing/chip-finish shape fill for density, not a standard-cell master. Related density goals, different mechanism (Technology DRCs).

Do FinFET / GAA nodes still need taps and endcaps?
Yes in spirit—well/substrate ties and boundary cells remain, though structures and rules change with the PDK. Learn roles, then read the node kit.

Can AOCV/POCV ignore decap?
Timing derates and IR are separate knobs. Decap changes voltage noise that can still move delay; close IR and STA together for hotspots.

Where should I read about latch-up itself?
Latch-up in CMOS covers the SCR device physics and test context; this post covers placement of the cells that prevent it.

Summary#

• Physical-only cells (taps, endcaps, fillers, decaps) enforce well bias, row-edge legality, site continuity and local decoupling—without RTL logic.
• Taps tie wells/substrate to rails on a foundry spacing grid; critical for latch-up and LVS.
• Endcaps close cell-row and abutment edges.
• Fillers pack leftover sites; they are not decaps or taps.
• Decaps add on-die C to fight dynamic IR; place by hotspot, not by superstition.
• Re-run physical-cell steps after ECOs; verify with DRC, LVS well ties, and static+dynamic IR.
• Map library cell names to these roles—exact masters are PDK-specific and often NDA.

Mastering physical-only cells turns “mysterious finishing DRCs” into a checklist you can debug under interview pressure and before tapeout. Use the linked latch-up, IR, DRC, PODE/CPODE and ECO posts when a failing marker points at wells, edges, density or voltage noise rather than a setup path.