Electromigration (EM) in VLSI: Black’s Equation, Limits and Fixes

A chip can pass every timing, DRC and LVS check, ship on schedule, and still fail in the field years later because a power rail or a clock wire slowly wore out. The usual culprit is electromigration (EM): the gradual movement of metal atoms in an interconnect, pushed along by the current flowing through it. EM does not show up on day one. It is a wear-out mechanism, so the design has to be built so that every wire and via stays below its current limit for the full product lifetime at the specified temperature.

For a physical design engineer, EM is a sign-off check like timing or IR drop, and it shapes the power grid, the clock tree, critical routes and late ECOs. This guide explains the physics in plain terms, Black's equation and the Blech effect, the difference between average, RMS and peak current limits, and then walks through illustrative calculations, where EM is checked in the flow, how to fix violations, a debug flowchart, interview questions, an FAQ and a summary.

Related reading: Power Ground Grid Insertion, VIAs in VLSI, Via Pillars: Timing and EM Guide and Metal Layers.

What electromigration is#

When current flows in a metal line, the conducting electrons collide with the metal atoms and transfer momentum to them. This is often called the electron wind. At low current density the effect is negligible. At the high current densities found in modern interconnects, which are very narrow and carry large currents, the electron wind is strong enough to make metal atoms drift slowly in the direction of electron flow (opposite to conventional current).

Damage happens where the atom flux is not uniform, so more atoms leave a region than arrive: at a via where the barrier metal blocks atom flow, at grain boundaries and at interfaces. Two failure signatures result:

• Voids form where atoms are depleted, usually at the cathode end (where electrons enter the line). A growing void raises resistance and can finally open the line or the via connection.
• Hillocks or extrusions form where atoms pile up, usually at the anode end. An extrusion can break through the dielectric and short to a neighbouring wire.

In copper interconnects the fastest diffusion path is generally the interface between the copper and the dielectric cap, rather than the grain boundaries that dominated in older aluminium wiring. That is one reason EM rules are always specific to a process and a layer.

Two points matter for design:

1. EM is statistical. Identical wires fail at different times, so foundry limits target a low failure probability over the lifetime, not the survival of the average wire.
2. EM is strongly temperature-dependent. Diffusion is thermally activated, so a hotter wire, including any self-heating, wears out much faster.

Black's equation#

The classic model for EM lifetime is Black's equation, published by J. R. Black in 1969:

MTTF = A × J^(−n) × exp( Ea / (k × T) ) MTTF : median time to failure A : constant depending on geometry and material J : current density in the conductor (A/cm²) n : current-density exponent (Black used 2) Ea : activation energy of the dominant diffusion path (eV) k : Boltzmann constant (8.617 × 10⁻⁵ eV/K) T : conductor temperature (K)

Three practical lessons come out of this simple formula:

• Lifetime falls faster than linearly with current density. With n = 2, doubling J cuts lifetime to a quarter. This is why widening a wire (which lowers J) is such an effective fix.
• Lifetime falls exponentially with temperature. A modest temperature rise can cost a large factor in lifetime, so the allowed current is lower at higher temperature.
• The parameters are process data. The foundry extracts A, n and Ea from accelerated stress tests and delivers the resulting current limits in the technology file or EM rule deck. Designers use those limits, not the equation directly.

JEDEC documents EM as one of the standard semiconductor failure mechanisms in JEP122 and describes an isothermal EM test procedure in JESD61 (both listed in the references).

The Blech effect: short wires can be immune#

As atoms pile up at the anode end and deplete from the cathode end, they build a mechanical stress gradient along the line. That stress pushes atoms back against the electron wind. In 1976, I. A. Blech showed that below a critical product of current density and line length, the back-stress balances the electron wind and net drift stops.

EM drift stops when J × L < (J × L)_critical

In practice this means a short wire segment between two vias can carry a higher current density than a long one without EM damage. Many foundry rule decks and sign-off tools apply a short-length or Blech relief: segments shorter than a specified length get a higher current limit or are exempt. Use it only exactly as the foundry rules allow.

Illustrative only: if a rule deck gave a critical product of 3,000 A/cm, a 10 µm segment (0.001 cm) would be immune up to 3,000 / 0.001 = 3 × 10⁶ A/cm², while a 100 µm segment would be immune only up to 3 × 10⁵ A/cm². The numbers are made up; the scaling with length is the point.

Average, RMS and peak current limits#

EM rules usually define three kinds of current limit for each layer and via type. Knowing which one a violation refers to tells you how to fix it.

Power nets carry current mostly in one direction, from the supply to the cells, so the average current is large and the average limit is the main check.

Signal nets are different. On a rising edge the driver charges the load through the wire; on a falling edge the load discharges back through the same wire in the opposite direction. The net DC flow is close to zero, and reversing current allows partial recovery of the damage. Signal EM rules are therefore usually more relaxed for average current than power rules, but the RMS current still heats the wire on every transition. Rule decks typically give separate limits or recovery factors for bidirectional current; follow your foundry's method.

Cell-internal EM is a third category. The currents inside a standard cell cannot be computed from the block layout, so library teams characterise the internal wiring and give limits as a function of input slew, output load and switching frequency. Sign-off tools then flag a cell instance whose operating condition exceeds its characterised limit.

Worked example 1: RMS current on a clock net (illustrative)#

All numbers here are made up to show the method. Real sign-off tools integrate the actual current waveform from extracted RC and library data.

A clock buffer drives a net segment with 200 fF of load at 0.75 V. The clock runs at 2 GHz (period 500 ps), and a clock toggles twice per cycle.

Charge per edge Q = C × V = 200 fF × 0.75 V = 150 fC One-way average I_avg = Q × f = 150 fC × 2 GHz = 0.30 mA (charging one way, the same amount discharging the other way) Approximate each charge/discharge as a 30 ps rectangular pulse: Peak current I_peak = Q / t_pulse = 150 fC / 30 ps = 5.0 mA Duty of the pulses 2 pulses × 30 ps / 500 ps = 0.12 RMS current I_rms = I_peak × √0.12 = 5.0 × 0.346 ≈ 1.73 mA

Suppose the rule deck allowed 1.2 mA RMS for this layer and width at the sign-off temperature (made-up limit). The segment is about 44 % over the limit. Options:

• Double the width with a non-default rule (NDR). The allowed current scales roughly with width, so the limit becomes about 2.4 mA and the segment passes. Cost: routing tracks and more coupling to neighbours, which you can manage with double spacing.
• Slow the edge. If the pulse stretches to 60 ps, peak drops to 2.5 mA and duty rises to 0.24, so I_rms = 2.5 × √0.24 ≈ 1.22 mA. It is still slightly over, and a slower clock edge hurts clock transition, insertion delay and jitter sensitivity. Usually a poor first choice for clock nets.
• Split the load. Drive half the sinks from a second buffer, so each segment carries roughly half the charge.

This is why teams avoid the very strongest clock buffers and use NDR width on clock trunks: clock nets toggle every cycle, so they are among the first nets to hit RMS limits. See Clock Tree Synthesis (CTS) and the CTS Spec File for where NDRs and buffer lists are defined.

Worked example 2: a power rail segment (illustrative)#

A group of high-activity cells on one standard-cell row draws 1.2 mA of average current from the row's power rail. The rail is fed by vertical straps on both sides, so in the simplest case the current splits and the worst rail segment next to each strap carries about 0.6 mA.

• Made-up rail limit at the sign-off temperature: 0.5 mA average. The segment fails by 20 %.
• Each strap-to-rail connection uses two via cuts with a made-up limit of 0.2 mA each, so 0.4 mA total. The vias fail too.

Fixes, in order of how cleanly they solve it:

1. Halve the strap pitch in that region. Each rail segment now feeds about half the current (about 0.3 mA), which passes, and IR drop improves as well.
2. Add via cuts at each strap crossing. Four cuts give 0.8 mA of capacity for the 0.6 mA (or 0.3 mA after fix 1).
3. Spread the hot cells with placement padding or a density screen so no single rail segment feeds such a dense cluster.

A real grid is a mesh solved by a power-grid analysis tool, but the lesson holds: power EM and IR drop share fixes and are closed together. See Decap Cells and Backside Power Delivery for related power-grid topics.

Worked example 3: why the sign-off temperature matters (illustrative)#

Take a toy Black's-equation model with n = 2 and Ea = 0.9 eV (illustrative values, not from any process). Compare a wire at 105 °C with the same wire at 125 °C:

Lifetime ratio = exp( Ea/k × (1/378.15 K − 1/398.15 K) ) = exp( 10,444 K × 1.328 × 10⁻⁴ K⁻¹ ) ≈ exp(1.39) ≈ 4.0

For the same current, the wire lasts about four times longer at 105 °C. To get the same lifetime at 125 °C, current density must fall by √4 = 2. So in this toy model, the allowed current at 125 °C is about half the allowed current at 105 °C. Running EM sign-off at the wrong temperature is one of the easiest ways to get a false pass.

Self-heating from RMS current (and, in FinFET and gate-all-around processes, from the devices) raises wire temperature further; foundries define how to include it.

Where EM is handled in the physical design flow#

• Floorplan and power planning. Strap width, pitch and layer choice, the number of via cuts from strap to rail, and power-switch placement set the power EM margin for the whole block. It is much cheaper to size the grid correctly here than to patch it later. See Floorplan.
• Placement. Dense high-power clusters concentrate current; density control and padding help both EM and IR drop.
• CTS. Clock buffer sizes, NDR width and spacing on trunks, and shielding are chosen with EM and SI in mind.
• Routing. Routers can honour EM-driven width rules for selected nets, insert redundant vias and use via pillars where the technology supports them. See Routing.
• Sign-off. Power EM is checked with static (average) and dynamic (vectorless or activity-driven) power-grid analysis. Signal EM is checked on the extracted netlist using switching activity, frequency, slews and the RC network. Commercial EM/IR tools such as Cadence Voltus and Ansys RedHawk-SC are typical examples.
• ECO. Timing ECOs that upsize drivers can create new EM violations, so re-check EM after every ECO.

Fixing EM violations#

• Widen the wire or apply an NDR. Lowers current density directly. Check tracks and coupling.
• Add via cuts or use via arrays. Vias are often the weakest point, especially single-cut vias on power connections.
• Promote to a thicker upper layer. Upper metals have more cross-section; remember the via stack down to the cell must also pass.
• Split the load or duplicate the driver. Reduces the current through each segment.
• Downsize the driver when it is much stronger than needed. Lower peak and RMS current, at the cost of slower transitions; re-check timing and max transition.
• Strengthen the grid for power EM: tighter strap pitch, wider straps, more vias. Gating idle logic (Clock Gating and ICG) also lowers average current.

Every fix interacts with timing, signal integrity and crosstalk, congestion or DRC, so fix in a multi-corner, multi-mode ECO environment and re-run all sign-off checks.

Debugging flow#

1. Check the inputs first. Wrong temperature, frequency, activity or EM rule file causes more false violations (and false passes) than real design problems.
2. Confirm short-length relief was applied where the foundry rules allow it.
3. Classify the violation (power, via, signal average/peak, signal RMS, cell-internal) and apply the cheapest fix that clears it with margin.
4. Re-run timing, SI, DRC and full EM/IR sign-off, because EM fixes often move the problem elsewhere.

Interview questions and answers#

Q1. What is electromigration? The gradual drift of metal atoms in an interconnect caused by momentum transfer from the conducting electrons. Flux divergence creates voids (opens, resistance rise) and hillocks (shorts) over time.

Q2. Write Black's equation and explain each term. MTTF = A · J^(−n) · exp(Ea / kT). J is current density, n is the current-density exponent (Black used 2), Ea is the activation energy, k is Boltzmann's constant and T is absolute temperature. Lifetime drops strongly with current density and exponentially with temperature.

Q3. What is the Blech effect? Back-stress from the atom concentration gradient opposes the electron wind. Below a critical J × L product, net drift stops, so short segments can tolerate higher current density.

Q4. Difference between average, RMS and peak EM limits? Average limits protect against classic drift from net DC current, mainly on power nets. RMS limits protect against Joule self-heating, mainly on high-activity signal and clock nets. Peak limits protect against very large instantaneous currents.

Q5. How do you fix a power EM violation? Reduce current per segment and via: tighter or wider straps, more via cuts, more power entry points, and spreading high-power cells. These also improve IR drop.

Q6. How do you fix a signal EM violation on a clock trunk? Use an NDR with wider wire (and double spacing for SI), split the load across more buffers, or move the trunk to a thicker layer. Avoid fixing it by weakening edges that the clock tree needs.

Q7. How is EM different from IR drop? IR drop is an immediate voltage loss that affects timing and function now. EM is a long-term wear-out that causes failure later. They share causes (high current in thin metal) and many fixes.

FAQ#

Is EM only a problem for power nets? No. Power nets are the most common place for average-current violations, but high-activity signal and clock nets hit RMS limits, and cell-internal EM depends on slew, load and frequency.

Can I waive EM violations on short wires? Only where the foundry rules give short-length or Blech relief and the tool applied it correctly. Do not waive by judgement.

Is EM the same as the antenna effect? No. The antenna effect is a manufacturing-time charge problem fixed with diodes or layer jumpers; EM is a lifetime wear-out problem fixed by lowering current density or temperature.

Summary#

• Electromigration is metal atom drift driven by current; voids cause opens and hillocks cause shorts over the product lifetime.
• Black's equation shows lifetime falls with current density (n ≈ 2 in Black's model) and exponentially with temperature.
• The Blech effect lets short segments tolerate higher current density, but only as the foundry rules allow.
• Power nets are limited by average current; signal and clock nets mostly by RMS (self-heating) and peak current.
• EM is designed in through the power grid, placement density, CTS NDRs and routing, then verified with EM/IR sign-off at the correct temperature, frequency and activity.
• Fix by lowering current density (wider wire, more vias, thicker layer, split load) and re-check timing, SI and DRC after every EM or timing ECO.

References#

• J. R. Black, "Electromigration—A brief survey and some recent results," IEEE Transactions on Electron Devices, vol. 16, no. 4, pp. 338–347, April 1969: https://doi.org/10.1109/T-ED.1969.16754
• I. A. Blech, "Electromigration in thin aluminum films on titanium nitride," Journal of Applied Physics, vol. 47, no. 4, pp. 1203–1208, 1976: https://doi.org/10.1063/1.322842
• J. Lienig, "Electromigration and its impact on physical design in future technologies," Proceedings of the 2013 ACM International Symposium on Physical Design (ISPD), pp. 33–40: https://doi.org/10.1145/2451916.2451925
• JEDEC JEP122, "Failure Mechanisms and Models for Semiconductor Devices": https://www.jedec.org/standards-documents/docs/jep-122e
• JEDEC JESD61, "Isothermal Electromigration Test Procedure": https://www.jedec.org/standards-documents/docs/jesd-61a01