IR Drop Analysis in VLSI: Static vs Dynamic IR Drop, Timing Impact and Fixes

Every standard cell on a chip is designed and characterized to run at a nominal supply voltage. The cell never actually sees that voltage. Current has to travel from the package, through bumps or pads, down a stack of metal straps and vias, and along thin rails to every cell, and every piece of that path has resistance. The voltage lost along the way is called IR drop, and a cell that sees less supply than its library assumed is slower than the timing report says.

This guide explains IR drop analysis in VLSI for physical design engineers: where the drop comes from, static versus dynamic IR drop, how analysis is set up and read, how IR drop feeds back into timing, and how to debug and fix hotspots. It includes illustrative worked examples, a debugging flowchart, interview questions and an FAQ.

Related reading: Power-Ground Grid Insertion, Decap Cells, Electromigration in VLSI and Power in VLSI Physical Design.

What IR drop is#

The power delivery network (PDN) is a large resistive mesh. A typical digital block has wide straps on upper metal layers, narrower straps on intermediate layers, and standard-cell rails on the lowest metal, all connected by via stacks. Current enters at the supply bumps or pads and leaves through the ground bumps or pads.

By Ohm's law, a current I through a resistance R loses a voltage I × R. Two drops matter for every cell:

• VDD drop: the supply at the cell's power pin is lower than the supply at the bump.
• VSS rise (ground bounce): the cell's ground pin sits above true ground, because return current also flows through a resistive network.

The cell sees the difference between the two, the effective voltage (check whether your budget refers to it or to each network separately):

V(effective) = V(VDD pin) − V(VSS pin) = Vnominal − (VDD drop + VSS rise)

Cells far from a bump, on thin rails, or in a region where many cells draw current at once see the largest drop. This is why IR drop maps usually show a "bowl" between bumps, with deeper spots where switching activity is concentrated.

Static IR drop and dynamic IR drop#

Static IR drop#

Static analysis treats the PDN as a purely resistive network and uses the average current of each instance over a period. The average comes from power analysis: leakage plus switching power from toggle rates (default activity, a SAIF file from simulation, or propagated activity). The tool solves a large linear system for the voltage at every node.

Static IR drop shows the steady-state weakness of the grid: too few straps, too few vias, too few bumps, or a region with unusually high average current. It is fast, so it runs from floorplan onwards to size the grid. It is also the starting point for electromigration checks on power wires, because the same currents set the current density in each strap and via.

Dynamic IR drop#

Real current is not flat. Most of it is drawn in short bursts just after clock edges, when flip-flops, clock buffers and the logic they drive switch together. Dynamic analysis models this in the time domain. Besides grid resistance it includes:

• Capacitance that can supply charge locally: intentional decap cells, the intrinsic capacitance of non-switching cells, and the capacitance of the grid itself.
• Package and board effects where a package model is available: inductance in bumps, balls and package planes, which resists fast changes in current.
• Switching scenarios: which cells switch together, and when.

The result is a voltage waveform at each instance. The worst dip (often reported as the minimum effective voltage within a cycle) is usually several times larger than the static drop at the same place, because the peak current is much larger than the average.

Vectorless versus vector-based dynamic analysis#

Dynamic analysis needs to know what switches:

• Vectorless: the tool assigns switching probabilities and builds its own worst-case-style scenario from timing windows and activity targets. It needs no simulation and gives good coverage, but the scenario may not match any real workload, so it can be either pessimistic or miss a specific pattern.
• Vector-based: activity comes from a gate-level or RTL simulation dump (for example a VCD or FSDB) of a chosen window, such as the highest-power interval of a test. It is realistic for that workload, but only as good as the chosen vectors.

Most sign-off flows use both: vectorless for coverage across the whole design, and vector-based for known high-power modes such as a test-pattern burst or a memory-intensive benchmark.

Other contributors you should know#

• Clock tree. Clock buffers switch every cycle with high activity, so the clock is often the largest single source of dynamic current. Clock gating lowers it; see Clock Gating and ICG.
• Scan shift. During test, many flops toggle every shift cycle, often far more than in functional mode. Dynamic IR drop in scan shift and capture is a known cause of test failures on otherwise good silicon, so test modes need their own analysis.
• Power-gated domains. When a domain wakes up, the inrush current through the power switch cells can disturb neighbouring always-on logic. Switch daisy-chaining and staged turn-on exist largely to control this. The switches also add resistance in series with the gated supply, so a gated domain sees extra static drop.

Worked example 1: static drop on a strap (illustrative)#

All numbers in this example are made up to show the arithmetic. They are not taken from any process or library.

A row of logic near the middle of a block draws an average of 40 mA from VDD. The resistance from the nearest VDD bump to that row, through the upper straps, via stacks and rails, is 0.5 Ω. The matching ground path back to a VSS bump is 0.4 Ω.

• VDD drop = 40 mA × 0.5 Ω = 20 mV
• VSS rise = 40 mA × 0.4 Ω = 16 mV
• Effective drop = 36 mV

At a nominal 0.75 V, that is 36 / 750 = 4.8% of the supply. Whether that passes depends entirely on the project's IR drop budget. If the budget for static drop were lower, the engineer would look at the largest resistance in the path first. If the report showed that a single via stack between the top straps and the intermediate layer contributed most of the 0.5 Ω, doubling the vias at that stack would cut the drop far more cheaply than adding a whole new strap. That is why via resistance, via counts and via pillars appear in IR drop debugging so often.

Worked example 2: a dynamic dip and decap (illustrative)#

Again, all numbers are invented.

After each rising clock edge, a dense cluster of flops and their fanout draws a burst of charge, about 2 pC, within roughly 100 ps. Over such a short time the grid and package cannot deliver much of it, because of their resistance and inductance, so most of the charge comes from capacitance near the cluster. With about 20 pF of local capacitance (decap cells plus intrinsic capacitance of quiet cells), a rough estimate of the dip is:

ΔV ≈ Q / C = 2 pC / 20 pF = 0.1 V

That is a large dip at 0.75 V. Doubling the local capacitance to 40 pF roughly halves it, to about 50 mV. Spreading the cluster over a larger area has a similar effect for a different reason: the same charge is then drawn from more rails and more nearby capacitance. The real waveform depends on how fast the grid recharges the capacitance, so this estimate only shows the direction and rough scale. Sign-off tools solve the full RC (and package RLC) network.

How IR drop affects timing#

Cell delay rises as supply voltage falls. At most operating points a lower effective voltage means slower cells. Ignoring IR drop is one way a design that is clean in STA can still fail at speed. There are three common ways to account for it:

1. Flat margin. Characterize or derate timing at a voltage below nominal that covers the expected drop. This is simple but pessimistic everywhere the real drop is small.
2. Voltage-aware (IR-aware) STA. Feed each instance's voltage from the IR analysis into STA, which then times each cell at its actual supply. This is accurate for the analyzed scenario; many flows combine it with a smaller flat margin.

Two subtleties catch people out:

• Clock paths matter for both setup and hold. If IR drop slows buffers in the capture clock branch more than in the launch branch, the capture edge arrives later. That helps setup but hurts hold. If it slows the launch branch more, the reverse happens. Dynamic drop that differs from cycle to cycle also adds jitter-like uncertainty to the clock. See Setup and Hold Violations for the basic checks.
• Lower voltage is not always slower. At low supply voltages in advanced nodes, temperature changes the relationship between voltage and delay, so corner choice matters. See Temperature Inversion in VLSI.

For the STA side of derates and margins, see Static Timing Analysis (STA) in VLSI.

Worked example 3: a path that fails only with IR-aware timing (illustrative)#

All numbers are made up. A register-to-register path closes with +12 ps setup slack in standard STA at the nominal corner voltage. With instance voltages from dynamic IR analysis applied, it reports −8 ps. The IR report shows that six cells on the data path sit in a hotspot with a worst effective drop well above the block average, next to a 64-bit register bank whose flops all switch on the same edge.

Reading the result:

1. The slowdown is concentrated in one region, not spread along the path. That points to a power problem rather than a logic problem.
2. The hotspot is caused by local current density (the register bank), not by a weak strap, because the static map of the same region looks normal.
3. Upsizing the path cells would draw even more current in the same spot.

The fix applied in the ECO run is to insert decap cells in the free sites around the register bank and to spread the bank's flops with cell padding. After re-running dynamic analysis and IR-aware STA, the path closes.

Where IR drop is handled in the flow#

IR drop is much cheaper to prevent than to repair after routing.

• Floorplan: plan bump or pad locations, macro placement and the grid pattern (strap widths, pitches and layers). Run an early static analysis with estimated currents. See Power-Ground Grid Insertion and Understanding of Metal Layers.
• Placement: avoid very dense clusters of high-activity cells. Many tools offer power- or IR-aware placement and density screens.
• CTS: limit clock buffer clustering, and use clock gating to reduce activity.
• Post-route: insert decap cells and fillers, run static and dynamic analysis on real parasitics, fix hotspots, and use IR-aware STA where required.
• Sign-off: analyze all relevant modes (functional, scan shift, scan capture, power-up of gated domains) at the appropriate corners, together with power-grid EM.

New PDN styles change the trade-offs. With backside power delivery, power moves to dedicated layers on the back of the wafer, which removes much of the front-side strap resistance and routing cost.

How to fix IR drop violations#

Two practical rules: find the cause before picking a fix, because grid resistance and local current density need different fixes, and re-run both IR and timing after every fix, because changing the grid, the placement or the cell sizes changes both.

Debugging IR drop violations#

1. Rule out connectivity problems first. A single instance with a drop far above its neighbours is often an open or weakly connected rail, a missing via, or a macro pin that is not tied to the grid. Many tools can report unconnected instances and high-resistance paths directly.
2. Separate static from dynamic. If the static map already shows the problem, the grid is too weak for the average current. If only the dynamic map shows it, the problem is peak current and local charge.
3. For static drop, find where the resistance is. A wide, shallow bowl between bumps points to strap width, pitch or bump count. A sharp step at one layer transition points to via count.
4. For dynamic drop, find what switches. Look at the instances drawing current in the dip: clock buffers, a register bank, a wide multiplexer, a scan chain segment. Spread them, add decap or reduce their activity.
5. Check the analysis setup. Wrong activity (for example default toggle rates on a block that is mostly idle), missing macro models or a missing package model can create or hide hotspots.
6. Check the timing impact. Run IR-aware STA, or check slack on paths through the hotspot. A hotspot under non-critical logic may be acceptable within the budget; one under a critical path or the clock tree is not.
7. Re-run static, dynamic, EM and timing after the fix.

Interview questions and answers#

Q1. What is IR drop? The voltage lost across the resistance of the power delivery network as current flows from the supply bumps or pads to the cells. It lowers the effective supply each cell sees.

Q2. What is the difference between static and dynamic IR drop? Static IR drop uses average current through a resistive network. Dynamic IR drop uses time-varying current and includes capacitance (decap, intrinsic cell capacitance) and, where modelled, package inductance. Dynamic drop captures the dips that follow clock edges.

Q3. What is effective voltage? VDD at the cell's power pin minus VSS at its ground pin. It combines the drop on the supply network and the rise on the ground network.

Q4. Why do decap cells help dynamic IR drop but not static IR drop? A decap stores charge and supplies it during short current bursts. It cannot supply a steady average current, which must come through the grid, so it does not change the static drop.

Q5. How does IR drop affect setup and hold? It slows cells. On a data path that hurts setup. On the clock tree, extra delay in the capture branch helps setup and hurts hold, and extra delay in the launch branch does the reverse.

Q6. What is vectorless dynamic analysis? Dynamic IR analysis where the tool builds its own switching scenario from activity targets and timing windows instead of a simulation dump. It gives broad coverage without simulation vectors.

Q7. Why is IR drop often worse during scan test? Scan shift toggles many flops every cycle, often far more than functional operation, so peak and average current can be much higher than in functional mode.

Q8. How are IR drop and electromigration related? Both come from current in the power network. Static and dynamic IR analysis produce the currents that EM checks compare against the current-density limits of each wire and via, so they are usually run together.

FAQ#

What is an acceptable IR drop? There is no universal number. Each project sets a budget, usually as a percentage of the nominal supply, often split into static and dynamic parts, and the timing corners or margins are chosen to match it. Use your project's budget, not a number from the internet.

Is ground bounce the same as IR drop? Ground bounce is the rise of the local ground above true ground. It is part of the effective drop. Inductance in the package and bumps adds an L·di/dt component on fast current changes, which dynamic analysis captures when a package model is included.

Can I fix IR drop by upsizing cells on the failing path? Usually not. Bigger cells draw more current in the same spot and can make the drop worse. Fix the grid or the local current first, then re-check timing.

Summary#

• IR drop is the voltage lost in the resistance of the power and ground networks. Each cell sees an effective voltage equal to its VDD pin minus its VSS pin.
• Static analysis uses average current and a resistive grid. Dynamic analysis uses time-varying current, decap, intrinsic capacitance and package effects, and shows the dips after clock edges.
• Activity drives the result. Choose vectorless or vector-based scenarios deliberately, and analyze test modes and power-up of gated domains as well as functional mode.
• IR drop slows cells and can break setup on data paths and hold or setup on clock paths. Account for it with margins, IR-aware STA, or both.
• Grid weakness calls for straps, vias and bumps. Local current density calls for decap, spreading and lower activity. Re-run IR, EM and timing after every fix.

References#

• N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison-Wesley, 2010 (sections on power distribution).
• M. Popovich, A. Mezhiba and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Springer, 2008.
• IR drop (overview): https://en.wikipedia.org/wiki/IR_drop
• Power network design (IC): https://en.wikipedia.org/wiki/Power_network_design_(IC)