Technology DRCs in VLSI: Width, Spacing, End-of-Line, Min Area, Enclosure and Density Rules

Every process technology comes with a set of geometric rules that a layout must obey before it can be manufactured: how narrow a wire may be, how close two shapes may sit, how far a metal must extend past a via, how small an island of metal may be, and how much metal any region of the chip may contain. These are technology design rules, and a check against them is a technology DRC (design rule check). For a physical design engineer, DRC is the last gate before tape-out, and the bulk of the work is not understanding a single rule but knowing which family a violation belongs to, why the tool created it, and which fix will not break something else.

This guide covers the main rule families, how they appear in the tech LEF versus the sign-off runset, where each kind shows up in the flow and how to debug them, with illustrative worked examples, a debugging flowchart, interview questions and an FAQ.

Related reading: Understanding Metal Layers, Pitch, Spacing and Offset, Vias in VLSI Physical Design and Routing in VLSI Physical Design.

DRC vs DRV: two different things#

The terms get mixed up in interviews and in reports, so it is worth separating them first.

• DRC (design rule check) is about geometry. It asks whether the drawn shapes on each mask layer can be manufactured reliably. A spacing error between two M2 wires is a DRC violation.
• DRV (design rule violation) in the timing and implementation sense is about electrical limits from the library and constraints: max transition, max capacitance and max fanout. These are covered in Design Rule Violations (DRVs) in VLSI.

Some tools also call routing violations "DRVs", so check which kind a report counts.

Where technology rules come from and where they live#

The foundry publishes a design rule manual (DRM) for each process. It describes every rule in words and pictures, with a value and often conditions such as width ranges or run lengths. The same rules are coded in two places that matter to a PD engineer:

1. The sign-off DRC runset. A deck for a physical verification tool (commercial tools such as Calibre, IC Validator or Pegasus, or open tools such as KLayout's DRC engine). This is the complete set of rules checked on the final GDS or OASIS data, including layers and conditions that the implementation tool never sees.
2. The technology LEF (or the tool's tech file). It holds the routing-relevant subset: layer widths, pitches, spacing tables, end-of-line rules, minimum area, via definitions and enclosures. The router uses these rules to build clean wires, and the implementation tool's own DRC check verifies against them.

This split explains one of the most common surprises in a project: a design that is clean in the router can still show violations in sign-off DRC. The router only knows what is in the LEF, works on abstract views of cells and macros, and may not model every conditional rule. Treat implementation-tool DRC as a fast filter and the sign-off runset as the truth.

Public open-source PDKs are a good way to see real rules without any NDA. The SkyWater SKY130 periphery rules, for example, list a metal1 minimum width and spacing of 0.140 µm, a minimum metal1 area of 0.083 µm², a larger spacing for "huge" (wide) metal1, and pattern-density limits checked over defined windows. The ASAP7 predictive PDK from Arizona State University and ARM Research provides a similar teaching view of a 7 nm FinFET rule set.

The main families of technology rules#

Minimum and maximum width#

Minimum width is the narrowest a shape may be drawn on a layer. Below it, lithography and etch cannot print the line reliably. Routers rarely break this rule on signal wires because they draw at the default width, but it appears around custom shapes, pin geometry and hand-edited ECOs.

Many processes also have a maximum width, or require slotting above a certain width, because very wide metal lines suffer from dishing during chemical-mechanical polishing (CMP) and from stress. This matters for power straps and wide buses: a strap drawn wider than the limit has to be split into several narrower straps.

Minimum spacing and width-dependent spacing#

Minimum spacing is the smallest gap between two shapes on the same layer. On modern nodes it is rarely a single number. The required spacing grows with the width of the wider shape and with the parallel run length (PRL), the distance over which the two shapes run side by side. A thin wire next to a wide power strap over a long run needs more space than two minimum-width wires.

In LEF, this is expressed with a spacing table. The values below are illustrative, not from any real process:

LAYER M2 TYPE ROUTING ; DIRECTION VERTICAL ; PITCH 0.28 ; WIDTH 0.14 ; AREA 0.083 ; MINENCLOSEDAREA 0.14 ; SPACINGTABLE PARALLELRUNLENGTH 0.00 0.50 1.50 WIDTH 0.00 0.14 0.14 0.14 WIDTH 0.40 0.14 0.20 0.28 WIDTH 1.50 0.14 0.28 0.50 ; SPACING 0.14 ENDOFLINE 0.20 WITHIN 0.05 ; END M2

To read the table, find the row for the wider of the two shapes and the column for their parallel run length; the cell gives the required spacing.

End-of-line (EOL) spacing#

The end of a narrow line prints with rounding and pull-back, so many processes require extra spacing in front of a line end. An EOL rule applies when the edge is narrower than a defined EOL width, and it checks a region extending ahead of (and slightly beside) that edge. In the LEF example above, SPACING 0.14 ENDOFLINE 0.20 WITHIN 0.05 means any edge shorter than 0.20 µm is a line end and needs 0.14 µm clearance in front of it, checked within 0.05 µm to each side. Real processes add further conditions, and EOL rules are among the most frequent post-route violations on the lowest metals.

Minimum area and minimum enclosed area#

A shape that is too small, such as a tiny metal patch under a via or a very short stub, may not print or may lift off. The minimum area rule sets a floor on the area of each isolated polygon. The minimum enclosed area (hole) rule sets a floor on the area of a gap fully surrounded by metal, which can appear when a router creates a small ring.

Minimum area violations are very common after ECOs, when a via landing or a short jog is left as a small isolated piece. The fix is usually to extend the metal along the preferred direction.

Enclosure (overlap) rules#

A via or contact must be surrounded by metal on the layers above and below it by a minimum enclosure (also called overlap or extension). Many processes use asymmetric rules: a small enclosure on all sides plus a larger enclosure on at least one pair of opposite sides, or "on one of two adjacent sides". SKY130's metal1 rules, for example, combine a 0.030 µm enclosure of the contact with a 0.060 µm requirement on one of two adjacent sides. Via definitions in the tech LEF encode these enclosures, so normal routing is clean; trouble comes from custom vias, rotated vias and vias dropped at wire ends.

Cut rules#

Via (cut) layers have their own rules: cut size (often only a few allowed sizes), cut-to-cut spacing, spacing to cuts on adjacent via layers, and limits on how many cuts can sit within a distance of each other. Multi-cut vias and via arrays in the power grid are the usual source of cut violations. If you use via pillars or ladders, they must also obey these rules; see Via Pillars in Physical Design.

Minimum step, notch and jog rules#

A minimum step rule limits how short an edge on a polygon outline may be. A notch is a narrow gap inside a single polygon, which is effectively a same-net spacing check. These rules catch small jogs and staircase shapes created when wires of different widths join or when pins are merged with routing.

Density rules#

CMP removes material at a rate that depends on the local pattern density. Too little metal in an area leads to erosion differences, and too much leads to dishing. Foundries therefore require the metal density of each layer to stay between a minimum and maximum within every window of a given size, checked as the window steps across the die.

• Low density is fixed by metal fill: dummy shapes that are electrically floating or tied, inserted after routing.
• High density cannot be fixed by fill. It needs fewer or narrower shapes, slotted straps or spreading of wide buses.

Fill adds capacitance to nearby nets, so timing sign-off should use extraction that includes fill or a fill-aware model.

Other rule families you will meet#

• Antenna rules limit the ratio of metal area connected to a gate during fabrication; see Antenna Effect in VLSI.
• Multiple patterning rules add same-mask spacing and coloring checks on tight-pitch layers; see Double Patterning in VLSI.
• Base-layer rules on wells, diffusion, poly and implants are mostly handled inside standard cells, but cell-edge and diffusion-break rules affect placement; see PODE vs CPODE.
• Latch-up and well-tap distance rules control how far any transistor may be from a well tap; see Tap Cell Placement and Latch-up in CMOS.
• Grid rules require every vertex to sit on the manufacturing grid. Off-grid shapes usually come from scaling, rotated macros or imported GDS.

Where DRC violations appear in the PD flow#

A large count is not always a large problem: thousands of hits of one rule in one macro are often a single systematic cause.

Worked example 1: minimum area on an ECO stub (illustrative)#

All numbers in the worked examples are illustrative, not from any foundry process.

Assume an M2 rule set with a minimum width of 0.14 µm and a minimum area of 0.083 µm². An ECO adds a via from M1 to M2 and a short M2 segment to connect to a neighbouring via. The router draws a 0.14 µm × 0.40 µm piece.

• Area = 0.14 × 0.40 = 0.056 µm², which is below 0.083 µm².
• Required length at minimum width = 0.083 / 0.14 ≈ 0.593 µm.

Fix: extend the segment along the preferred direction to at least about 0.60 µm (rounded up to the manufacturing grid), checking that the extension does not create an EOL or spacing problem with the next shape. Most routers have a minimum-area fixing option for exactly this case.

Worked example 2: a signal next to a wide strap (illustrative)#

Using the illustrative spacing table above, a 1.6 µm wide M2 power strap runs beside a minimum-width signal wire for 2.0 µm. The wider shape is 1.6 µm, so use the WIDTH 1.50 row. The parallel run length is 2.0 µm, so use the 1.50 column. Required spacing: 0.50 µm.

The signal was placed on the first track next to the strap at 0.14 µm spacing, which is legal for minimum-width neighbours but not here. Options:

1. Move the signal at least 0.50 µm from the strap.
2. Shorten the parallel run so a smaller column applies.
3. Add a routing blockage or keep-out next to straps so the router never uses the first track; see Blockages in VLSI.

If the router's tech file has the spacing table, this error should not appear. When it does, check whether the tech LEF is out of date versus the runset.

Worked example 3: density in one window (illustrative)#

A layer has a maximum density of 77% checked in 50 µm × 50 µm windows (2,500 µm² each). A window over a wide data bus contains 2,150 µm² of metal, which is 86%.

• Maximum allowed metal = 0.77 × 2,500 = 1,925 µm².
• Excess = 2,150 − 1,925 = 225 µm².

Fill cannot help. You need to reduce metal: slot or split the widest straps, move part of the bus to another layer, or spread it over a larger area. In a neighbouring empty window at 12% where the minimum is 20%, the fill tool adds dummy metal to reach at least 500 µm².

Debugging and fixing technology DRCs#

1. Run the right checker. Run sign-off DRC on the merged GDS, not only the implementation-tool check. Make sure the runset version matches the PDK version used for the LEF.
2. Group by rule and layer. Sort the results by rule name, then by count. One rule with thousands of hits is usually systematic.
3. Look at the location pattern. Violations on a regular grid point to the power grid or a via array; violations inside one macro point to its GDS; violations at cell boundaries point to placement or the library; scattered violations in hot spots point to congestion.
4. Ask whether the router knew the rule. If the rule is not in the tech LEF, the router cannot avoid it. Update the LEF or tool settings, or add guard spacing or blockages.
5. Fix systematic causes at the source. Regenerate PG vias, adjust strap width or pitch, fix the macro abstract, change fill settings.
6. Fix random violations locally. Use the router's search-and-repair or ECO route, reroute the affected nets, or spread cells in the congested area.
7. Re-run everything affected. Geometry fixes can change parasitics, antenna ratios and density. Re-run DRC, extraction, timing and, where needed, LVS.

Interview questions and answers#

Q1. What is the difference between DRC and DRV? DRC checks geometric manufacturing rules on the layout, such as width, spacing and enclosure. DRVs are electrical limits such as max transition, max capacitance and max fanout. A design can be DRC-clean with DRVs, and the reverse.

Q2. Why can a design be clean in the P&R tool but fail sign-off DRC? The router works with the tech LEF, which holds only a subset of the rules, and with abstract views of cells and macros. Sign-off DRC checks the full runset on real GDS geometry, including conditional rules, base layers, fill and merged IP.

Q3. What is an end-of-line rule? A rule requiring extra clearance in front of the end of a narrow line, because line ends round and pull back during patterning. It applies to edges shorter than a defined EOL width.

Q4. What causes minimum area violations and how do you fix them? Small isolated metal pieces, usually via landings or short stubs created by routing or ECOs. Fix them by extending the metal in the preferred direction to meet the area, then rechecking spacing.

Q5. Why are density rules needed? CMP removal depends on local pattern density. Too little or too much metal in an area leads to thickness variation, dishing and erosion. Min and max density limits per window keep the surface planar.

Q6. Can metal fill fix a maximum density violation? No. Fill only adds metal. Maximum density violations need less metal in that window, for example by slotting wide straps or moving routes.

Q7. How do you approach 50,000 DRC violations after first route? Group them by rule, layer and location. Usually a few systematic causes account for most of them, such as a PG via array, a bad macro abstract or a missing LEF rule. Fix those at the source first, then clean the remaining random violations with ECO routing.

FAQ#

Can DRC violations be waived? Some can, only through a formal process agreed with the foundry, usually for known, characterized structures in qualified IP. Signal routing violations are normally fixed, not waived.

What is the difference between DRC and LVS? DRC checks that the shapes can be manufactured. LVS (layout versus schematic) checks that the shapes form the circuit described by the netlist. A design must pass both.

Do DRC fixes affect timing? They can. Moving wires changes coupling, extending stubs adds a little capacitance, and fill adds capacitance to nearby nets. Always re-extract and re-time after a large DRC cleanup.

Summary#

• Technology DRCs check that layout geometry can be manufactured: width, spacing, end-of-line, area, enclosure, cut, step and density rules, plus antenna, multi-patterning and base-layer rules.
• The DRM defines the rules, the sign-off runset checks all of them, and the tech LEF gives the router a subset. Router-clean is not sign-off clean.
• Spacing on advanced nodes depends on width and parallel run length; EOL and minimum area rules dominate post-route cleanup on the lower metals.
• Low density is fixed with fill; high density needs less metal.
• Debug by grouping violations by rule, layer and location, fix systematic causes at the source, then clean random ones locally and re-run DRC, extraction and timing.

References#

• Design rule checking (overview): https://en.wikipedia.org/wiki/Design_rule_checking
• SkyWater SKY130 open-source PDK, periphery design rules: https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html
• KLayout DRC reference manual: https://www.klayout.de/doc/manual/drc.html
• L. T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthy and G. Yeric, "ASAP7: A 7-nm finFET predictive process design kit," Microelectronics Journal, vol. 53, 2016: https://doi.org/10.1016/j.mejo.2016.04.006
• Chemical-mechanical polishing (background on why density rules exist): https://en.wikipedia.org/wiki/Chemical-mechanical_polishing