Latch-up in CMOS: Parasitic SCR, Triggers, Prevention and JESD78 Testing

Latch-up is one of the oldest failure modes in CMOS and still one of the most destructive. A short burst of current or an overvoltage at the wrong place switches on a parasitic thyristor hidden inside every bulk CMOS layout. Once it turns on, it creates a low-resistance path from VDD to VSS that stays on until power is removed. If the supply can deliver enough current, the chip heats up, metal fuses, and the part is damaged for good. If it survives, you still get a system that hangs and draws far too much current until someone power-cycles it.

This guide explains latch-up the way a physical designer or layout engineer needs it: the PNPN mechanism, what triggers it, what trigger and holding voltage and current mean, how well taps, tap-cell spacing and guard rings prevent it, how SOI and FinFET change the picture, how parts are tested under JEDEC JESD78, and the layout and PD checks you should run. It ends with a debug flowchart, interview questions, an FAQ and a summary.

Related reading: Tap Cell Placement in VLSI, Antenna Effect in VLSI, and PODE vs CPODE and cell edges.

The parasitic PNPN structure#

Take a standard CMOS inverter on a p-type substrate with an n-well for the PMOS. Look at the cross-section and four regions line up between VDD and VSS:

• the p+ source of the PMOS (tied to VDD),
• the n-well,
• the p-substrate,
• the n+ source of the NMOS (tied to VSS).

That is a p-n-p-n stack: a thyristor, also called a silicon-controlled rectifier (SCR). It can be drawn as two bipolar transistors:

• Q1, a vertical PNP: emitter = PMOS p+ source, base = n-well, collector = p-substrate.
• Q2, a lateral NPN: emitter = NMOS n+ source, base = p-substrate, collector = n-well.

Two resistors complete the model:

• R_well: the resistance of the n-well between the PNP base and the well tap (n+ to VDD).
• R_sub: the resistance of the substrate between the NPN base and the substrate tap (p+ to VSS).

Why it latches: positive feedback#

In normal operation both parasitic transistors are off. Their base-emitter junctions are held at zero bias because the well is tied to VDD and the substrate to VSS through the taps.

Now suppose some current flows into the substrate, for example from an I/O pin that undershoots below VSS. That current flows through R_sub to the substrate tap. The I·R drop raises the local substrate potential. If it rises by roughly one base-emitter turn-on voltage (around 0.6 to 0.7 V for silicon at room temperature), Q2 starts to conduct.

Q2's collector is the n-well. Q2 pulls current out of the well, through R_well, which lowers the local well potential below VDD. That forward-biases Q1's emitter-base junction, so Q1 turns on. Q1's collector is the substrate, so Q1 injects even more current into the substrate, which turns Q2 on harder.

That is a positive feedback loop. In the simplest model, ignoring the shunt resistors, the loop sustains itself when the product of the two current gains is at least one:

β_npn × β_pnp ≥ 1

The shunt resistors R_well and R_sub steal base current from the transistors, so the real condition is stricter: lower shunt resistance means more current is needed before the loop can close. This is the core idea behind almost every prevention technique: lower R_well and R_sub, lower the bipolar gains, or keep the triggering current away.

Trigger point and holding point#

Plot the current through the PNPN structure against the voltage across it and you get the classic snapback curve:

1. Blocking region: at low current the structure blocks; only leakage flows.
2. Trigger point (V_t, I_t): enough current or voltage turns the loop on.
3. Snapback: the voltage across the structure collapses while the current rises.
4. Holding point (V_h, I_h): the minimum voltage and current that keep the structure latched.

Two conditions decide whether a latch-up event is sustained:

• the holding voltage V_h is below the supply voltage across the structure, and
• the supply can deliver more than the holding current I_h.

If either is false, the structure falls back out of latch-up when the trigger goes away. That is why designers talk about holding voltage so much: if V_h can be kept above the supply voltage, the structure may trigger briefly but cannot stay latched from that supply. It is also why low-voltage core supplies are generally less exposed than higher-voltage I/O and analog supplies. Do not assume immunity from that, though: the real numbers depend on the process, temperature and layout, and must come from the foundry's characterisation.

What triggers latch-up#

Anything that injects enough carriers into the well or substrate, or forward-biases the emitter junctions, can trigger the loop.

• I/O overshoot and undershoot. A signal pin driven above VDD forward-biases the p+/n-well junction of the output PMOS drain and injects holes; a signal driven below VSS forward-biases the n+/p-sub junction of the NMOS drain and injects electrons. Ringing on long board traces and hot-plugging are classic causes.
• Supply overvoltage and transients. Spikes on VDD increase junction leakage and can cause breakdown that triggers the loop.
• Power-up sequencing. If an I/O is driven while its own supply is still off, or one supply domain comes up before another, junctions can be forward-biased through the ESD diodes and the I/O devices.
• Fast dV/dt on supplies. The well-to-substrate junction is a large capacitor. A fast VDD ramp pushes displacement current (C·dV/dt) through the well and substrate resistances.
• ESD events. ESD clamps and diodes inject large currents into the substrate nearby; poorly isolated ESD structures can trigger latch-up in neighbouring logic.
• Radiation. A heavy-ion strike creates a column of charge that can trigger the loop: single-event latch-up (SEL), a key concern for space and high-reliability parts.
• Temperature. Higher temperature lowers the base-emitter turn-on voltage, raises bipolar gain and increases well and substrate resistance, all of which make latch-up easier. JEDEC's JESD78 test method notes that elevated temperature reduces latch-up resistance.

Worked example 1: tap spacing and trigger current (illustrative)#

All values are made up to show the trend; real values come from your process.

Suppose an injected current flows through the substrate to the nearest substrate tap through an effective resistance R_sub. The NPN turns on when I_inj × R_sub ≈ 0.7 V.

• Taps far apart, R_sub = 1.4 kΩ: I_trigger ≈ 0.7 V / 1.4 kΩ = 0.5 mA
• Tap spacing halved, R_sub ≈ 0.7 kΩ: I_trigger ≈ 1.0 mA
• Guard ring added close to the injector, R_sub ≈ 0.2 kΩ: I_trigger ≈ 3.5 mA

The relationship is roughly inverse: the shorter and wider the path to a tap, the more current the structure can absorb before it turns on. Resistance is not exactly linear with distance in a real 3-D substrate, so this is for intuition only. It is also why tap-cell distance rules exist, and why I/O areas, which see the largest injected currents, get much more aggressive protection than core logic.

Worked example 2: holding voltage vs supply (illustrative)#

Assume a parasitic SCR in a given layout has V_h = 1.2 V and I_h = 5 mA.

• On a 0.75 V core supply, the supply cannot hold the structure on, because V_h > VDD. A trigger may cause a short current spike but the structure falls out of latch-up when the trigger ends.
• On a 1.8 V I/O supply, V_h < VDD. If the supply can deliver more than 5 mA, which a board supply easily can, a trigger causes a sustained latch-up.

Lesson: latch-up risk depends on the supply that feeds the structure, not only on the layout. Check every supply domain separately, especially I/O, analog and higher-voltage domains.

Prevention techniques#

1. Well and substrate taps#

The single most important rule: tie every well and substrate region to its supply often enough. Taps keep R_well and R_sub low, so injected current is collected before it can forward-bias the base-emitter junctions.

Many modern standard-cell libraries are tapless: the cells do not include their own well and substrate ties. Instead, the physical design flow inserts tap cells (well-tap cells) on a regular pattern, often a staggered or checkerboard arrangement, so no point in any row is farther from a tap than the foundry's maximum tap-to-tap distance. Endcap or boundary cells at row ends are also part of the scheme. See our Tap Cell Placement post for how tap insertion works in a P&R tool.

2. Guard rings#

A guard ring is a continuous diffusion ring tied to a supply around a device or a block:

• a p+ ring tied to VSS in the substrate around NMOS devices collects holes and keeps the local substrate at VSS;
• an n+ ring (or n-well ring) tied to VDD around PMOS devices or around a sensitive block collects electrons.

I/O drivers, ESD structures and anything that connects to the outside world are usually surrounded by double guard rings (one of each type) and kept a minimum distance away from core logic. The foundry's I/O and latch-up rules define where rings are mandatory and how wide and far they must be.

3. Spacing between NMOS and PMOS#

Increasing the spacing between n+ diffusion in the substrate and the n-well edge (and between p+ in the well and the well edge) lowers the gain of the lateral NPN and increases the trigger point. It costs area, so it is used mainly where rules require it: I/O, ESD and analog regions.

4. Process measures#

At the process level, foundries reduce latch-up susceptibility using techniques such as retrograde wells (higher doping deeper in the well, lowering R_well), epitaxial layers on heavily doped substrates (lowering R_sub), deep trench isolation and controlled carrier lifetime. As a designer you do not choose these, but they explain why latch-up rules differ between technologies.

5. Circuit and system measures#

• Clamp I/O pins so overshoot and undershoot stay within the absolute maximum ratings.
• Use current-limiting series resistors on inputs exposed to the outside world.
• Define and verify power sequencing, especially for multi-supply chips.
• Use ESD protection that is designed with latch-up in mind, and keep ESD clamps away from sensitive core logic or separate them with guard rings.

SOI, FinFET and advanced nodes#

SOI (silicon-on-insulator). In SOI, each transistor sits on a buried oxide, and devices are laterally isolated by oxide. The vertical path between the PMOS well and the substrate under the NMOS that forms the bulk PNPN does not exist in the same way, so classical bulk latch-up is largely eliminated within fully isolated SOI devices. JEDEC JESD78F still lists "some Silicon-On-Insulator (SOI)" technologies as in scope, so SOI parts are still tested. Body-tied structures, substrate contacts and I/O regions can still contain parasitic paths.

Bulk FinFET. Bulk FinFET processes still have n-wells, p-wells and a substrate under the fins, so the parasitic PNPN still exists, and taps and tap-distance rules still apply. Fin geometry, shallow trench isolation and well doping change the resistances and gains compared with planar CMOS. The details are process-specific: follow the foundry's latch-up rules rather than older rules of thumb.

Low core voltages. As noted above, core supplies below the holding voltage are less exposed to sustained latch-up, but I/O and analog supplies are not, and process-dependent holding voltages must be checked, not assumed.

Latch-up testing: JEDEC JESD78#

The industry qualification test is JEDEC JESD78, "IC Latch-Up Test". At the time of writing, the current revision listed by JEDEC is JESD78F.02 (November 2023) (JEDEC). According to the standard's foreword and scope:

• It defines two stress types: a Signal Pin Test (current injection into signal pins) and a Supply Test (overvoltage on supply pins).
• Current injection can be done as an I-Test (forcing current with a voltage compliance limit) or an E-Test (forcing voltage with a current compliance limit). The E-Test option was introduced in revision F; the term comes from AEC-Q100-004, the automotive latch-up test.
• It defines preconditioning, the stress pulse, latch-up detection and failure criteria.
• It applies to NMOS, CMOS, bipolar and combinations of these, including some SOI.

Earlier revisions such as JESD78D (JEDEC PDF) defined Class I testing at room temperature and Class II at the maximum rated operating temperature, and set the overvoltage stress at 1.5 × VDD or the maximum stress voltage, whichever is less. Check the current revision for exact current levels, classes and conditions before you write a spec. JEDEC also published JEP193 (January 2023), a survey of how the industry applies JESD78E with recommendations for improvement (JEDEC).

For physical designers the takeaway is simple: the test injects current into every signal pin and overvoltage on every supply. Every I/O and every supply domain is a potential trigger, so the I/O ring and its neighbourhood need the most protection.

Layout and physical design checks#

1. Tap insertion and tap-distance DRC. Run the foundry's tap rules after placement and again after every ECO. Upsizing or moving cells can open gaps.
2. Endcap and boundary cells. Check that every row end and macro edge has the required cells.
3. Latch-up rule deck. Foundries provide latch-up rules in the DRC deck, often as optional or I/O-specific checks: guard ring presence, spacing from injectors to opposite-type devices, tap coverage. Make sure they are enabled.
4. Electrical rule checks. Programmable ERC tools (for example Calibre PERC) can check topology-based rules such as which devices are near I/O injectors, missing guard rings on specific pin types, and cross-domain connections.
5. I/O ring rules. Follow the I/O library's integration guide: spacing between I/O and core, mandatory rings, and filler and corner cells.
6. Multi-voltage boundaries. At power-domain boundaries, wells at different potentials sit close together. Check well spacing and level-shifter placement rules.
7. Macros and analog blocks. Third-party IP must come with its own latch-up rule compliance; check boundaries where IP meets your logic.
8. Post-ECO. Late metal-only ECOs usually do not affect taps, but cell-level ECOs can. Re-run tap checks.

Debugging and fixing latch-up#

1. Locate the site. Use thermal imaging, emission microscopy or the failing pin and supply from the test report to find where current flows.
2. Check taps near the site. Missing or distant taps are the most common layout cause. Add taps and confirm the tap rule.
3. Check for an injector next to an opposite-type device. An I/O driver, ESD diode or analog device close to core logic without rings is a classic cause. Add guard rings or increase spacing.
4. Check mixed-supply boundaries. Where an I/O or high-voltage domain meets core logic, use double rings and separate the supplies.
5. Check power sequencing. If latch-up only happens during power-up, fix the sequence or add clamps.
6. Re-run the latch-up checks and the test.

Interview questions and answers#

Q1. What is latch-up in CMOS? A low-impedance path between VDD and VSS caused by a parasitic PNPN thyristor turning on and staying on through positive feedback, until power is removed.

Q2. Which parasitic transistors form the SCR? A vertical PNP (PMOS p+ source, n-well, p-substrate) and a lateral NPN (NMOS n+ source, p-substrate, n-well), with well and substrate resistances as shunts.

Q3. What is the condition for latch-up to be sustained? Loop gain of at least one (β_npn × β_pnp ≥ 1 in the simple model), the holding voltage below the supply voltage, and the supply able to provide more than the holding current.

Q4. How do tap cells prevent latch-up? They tie the well and substrate to their supplies at regular intervals, keeping the well and substrate resistances low so injected current is collected before the base-emitter junctions forward-bias.

Q5. What is a guard ring? A continuous diffusion ring tied to a supply around a device or block. It collects injected carriers and keeps the local well or substrate potential fixed.

Q6. Why are I/O cells more sensitive to latch-up? They connect to external signals that can overshoot or undershoot, and they see ESD and hot-plug events, so they inject the most current.

Q7. Does SOI have latch-up? Classic bulk latch-up is largely eliminated within fully isolated SOI devices because the buried oxide isolates them, but some structures and I/O regions can still have parasitic paths, and SOI parts are still tested.

Q8. Which standard defines latch-up testing? JEDEC JESD78 (current revision JESD78F.02), with the Signal Pin Test and Supply Test; automotive parts also use AEC-Q100-004.

Q9. Why does temperature matter? Higher temperature lowers the turn-on voltage and raises bipolar gain and resistance, so latch-up triggers more easily.

FAQ#

Is latch-up the same as ESD damage? No. ESD is a very short, high-energy discharge; latch-up is a sustained high-current state. An ESD event can trigger latch-up, and both are qualified with separate tests.

Can latch-up happen without permanent damage? Yes. If the current is limited, the chip may only hang and draw excess current until power-cycled. JESD78's foreword itself notes that latch-up may or may not cause physical damage.

Why do modern libraries need separate tap cells? Removing taps from every cell saves area. The taps are placed separately at the spacing the process requires.

Do I need guard rings around standard cells? Usually not for core logic, where tap cells and the foundry's rules are enough. Rings are typically required for I/O, ESD and analog devices, and at certain domain boundaries.

Does the clock tree or timing affect latch-up? Not directly, but large simultaneous switching causes supply bounce, and the I/O drivers that see the most overshoot are often the fastest ones. Keep supply integrity in mind. See our Static Timing Analysis guide for timing basics.

Summary#

• Bulk CMOS contains a parasitic PNPN thyristor between VDD and VSS, made from a vertical PNP and a lateral NPN.
• Injected current through the well or substrate resistance forward-biases a base-emitter junction and starts a positive-feedback loop.
• The latched state is sustained only if the holding voltage is below the supply and the supply can provide more than the holding current.
• Prevention comes down to low well and substrate resistance (taps, tap-cell spacing, guard rings), spacing, process measures, and controlling triggers (clamps, sequencing).
• JEDEC JESD78F.02 tests current injection into signal pins and overvoltage on supplies; every I/O and supply domain is a potential trigger.
• In PD, check tap rules, endcaps, the latch-up DRC and ERC decks, I/O ring rules and domain boundaries after every placement change.

References#

• JEDEC, JESD78F.02 "IC Latch-Up Test" (Nov 2023): https://www.jedec.org/standards-documents/docs/jesd-78b
• JEDEC, JESD78D "IC Latch-Up Test" (Nov 2011, earlier revision): https://www.jedec.org/sites/default/files/docs/JESD78D.pdf
• JEDEC, JEP193 "Survey On Latch-Up Testing Practices and Recommendations for Improvements" (Jan 2023): https://www.jedec.org/standards-documents/docs/jep193