Signoff

ECO (Engineering Change Order) in VLSI physical design explained: timing, DRV, noise, leakage and functional ECOs, pre-mask vs post-mask (metal-only) changes, spare cells, the sign-off STA to place-and-route ECO loop, what to re-verify after every ECO and how to debug an ECO that will not converge, with illustrative examples and interview Q&As.

IR drop analysis in VLSI explained for physical design engineers: where supply and ground drop come from, static vs dynamic IR drop, vectorless and vector-based analysis, how IR drop affects setup and hold, and how to debug and fix hotspots, with illustrative examples, a flowchart and interview Q&As.

What technology DRCs check and why: width, width- and run-length-dependent spacing, end-of-line, minimum area, enclosure, cut, notch and density rules, how the tech LEF differs from the sign-off runset, and how to debug DRC violations, with illustrative examples, a flowchart and interview Q&As.

What electromigration is, Black's equation and the Blech effect, average vs RMS vs peak current limits, worked examples for clock and power nets, where EM is handled in the physical design flow, and how to debug and fix EM violations.

Why cell delay can fall as temperature rises at low supply voltage, how mobility and threshold voltage compete, and what temperature inversion means for STA corners, hold sign-off, DVFS modes and timing fixes.

Latch-up in CMOS explained for physical designers: the parasitic PNPN (SCR) mechanism, triggers, holding voltage and current, tap cells and guard rings, SOI/FinFET, JEDEC JESD78 testing, layout checks and interview questions.