OCV, AOCV and POCV in STA: Derates, CRPR and Sign-off

OCV, AOCV and POCV in STA explained: flat derates, AOCV tables, POCV variation, CRPR/CPPR, worked examples, debug flow and interview Q&As for sign-off.

OCV, AOCV and POCV in STA: Derates, CRPR and Sign-off
On this page 10 sections
  1. Why on-chip variation needs derates
  2. Flat OCV and set_timing_derate
    1. Worked example A: flat OCV on setup (illustrative)
  3. Graph-based AOCV: depth, distance and less blanket pessimism
    1. Worked example B: AOCV vs flat on a long path (illustrative)
  4. Parametric / statistical POCV
  5. CRPR / CPPR: common path pessimism removal
    1. Worked example C: derates + CRPR credit (illustrative)
  6. Interaction with uncertainty, SI, IR and useful skew
  7. Debug flowchart: “OCV is killing my slack”
  8. Interview Q&As
  9. FAQ
  10. Summary

On-chip variation (OCV) is why a single “typical” delay is never enough for sign-off STA. Process, voltage and temperature are not uniform across a die: two identical cells a millimetre apart can be slower or faster than each other on the same wafer. STA models that uncertainty with derates—and with successively more refined models called flat OCV, AOCV (advanced / graph-based OCV) and POCV (parametric / statistical OCV). CRPR (common path pessimism removal, also called CPPR) then peels back the double-counting that early/late analysis would otherwise apply on shared clock nets.

This post is a practitioner guide: what each model means, how early/late derates hit setup and hold, how AOCV tables and POCV moments reduce blanket pessimism, why CRPR exists, how derates interact with uncertainty, SI and IR, plus an illustrative slack walk-through, a debug flowchart and interview Q&As. Related reading: Static Timing Analysis (STA) in VLSI, Setup and Hold Violations, Useful Skew in VLSI, Recovery and Removal in STA, Multicycle Path and False Path in STA, Clock Tree Synthesis (CTS), ECO in VLSI Physical Design, IR Drop Analysis in VLSI, Temperature Inversion in VLSI and Crosstalk in VLSI.

Why on-chip variation needs derates#

Global PVT corners (slow/fast process, high/low voltage, hot/cold temperature) already bound chip-to-chip and lot-to-lot spread. They do not fully cover spatial mismatch inside one die: random dopant fluctuation, local layout effects, IR gradients, temperature gradients and residual modelling error on short nets. If you only use a single max delay for every cell in a setup check, you understate the chance that the launch path is slower than the capture path relative to each other. If you use a single min delay for hold, you understate the opposite race.

Derates are the classical STA answer: stretch the delay you fear and shrink the delay that helps you. For setup, that means late data / late capture clock and early launch clock. For hold, that means early data / early capture clock and late launch clock. The multipliers (or additive margins) come from the foundry/library methodology as flat constants, AOCV tables indexed by path depth and distance, or POCV/LVF-style statistical moments. Exact table numbers are NDA; everything numeric below is illustrative.

Flat OCV and set_timing_derate#

Flat (or “constant”) OCV applies the same early and late factors to qualifying delays, independent of path length. In SDC-style form (syntax varies by tool):

Code
# Illustrative — not a real foundry recipe set_timing_derate -early 0.95 set_timing_derate -late 1.05 # Often refined with -clock / -data / -cell_delay / -net_delay scopes

Interpretation for a setup check on a rising-edge to rising-edge path:

Data table
Path segment Setup view Why
Launch clock network Early Makes the launch edge arrive sooner → less time for data
Data / combinational path Late Makes data arrive later at the capture D pin
Capture clock network Late Makes the capture edge arrive later → more required time pressure
Library setup requirement Usually not derated the same way as path delays (methodology-specific) Read your flow docs

For hold, flip early/late on those segments. The same physical clock buffer can therefore be treated as early in one check and late in another—that is intentional pessimism, and it is exactly what CRPR later softens on the common portion of the clock tree.

Figure 1. Flat OCV early/late derates on launch vs capture paths (illustrative).

Worked example A: flat OCV on setup (illustrative)#

All numbers are made up for teaching.

  • Period (T = 1.0\,\text{ns})
  • Ideal clock root; launch clock delay (nominal) (200\,\text{ps}), capture clock delay (220\,\text{ps})
  • Data path delay (nominal) (650\,\text{ps})
  • Library setup (T_{su} = 40\,\text{ps})
  • Flat derates: early (0.95), late (1.05)
  • Clock uncertainty (30\,\text{ps}) (setup)

Without OCV (ignoring uncertainty for a moment):
data required time ≈ (T + T_{\text{clk,cap}} - T_{su} = 1000 + 220 - 40 = 1180\,\text{ps})
data arrival ≈ (T_{\text{clk,launch}} + T_{\text{data}} = 200 + 650 = 850\,\text{ps})
slack ≈ (1180 - 850 = +330\,\text{ps}).

With flat OCV for setup:
launch clock early: (200 \times 0.95 = 190\,\text{ps})
data late: (650 \times 1.05 = 682.5\,\text{ps})
capture clock late: (220 \times 1.05 = 231\,\text{ps})
arrival ≈ (190 + 682.5 = 872.5\,\text{ps})
required ≈ (1000 + 231 - 40 - 30 = 1161\,\text{ps})
slack ≈ (1161 - 872.5 = +288.5\,\text{ps}).

The absolute slack is still positive, but OCV + uncertainty ate tens of picoseconds. On a critical path those tens decide ECO scope. See setup and hold for the underlying check equations.

Graph-based AOCV: depth, distance and less blanket pessimism#

Advanced OCV (AOCV) replaces one global early/late pair with a table (or set of tables) indexed by metrics such as:

  • Path depth — number of stages (or a similar depth metric) in the path being derated
  • Distance — spatial separation between launch and capture (or between the nets being compared)

The physical intuition: random variation tends to average out along a long chain of uncorrelated stages, and two distant points may share less correlated global shift than two neighbours—or the table may encode a foundry-chosen compromise of both effects. In practice the library/methodology team ships tables; STA looks up a derate for the path’s depth and distance rather than always applying the worst short-path factor.

Graph-based AOCV typically computes a single depth/distance context per arc or per path endpoint in the timing graph and applies the looked-up derate during graph analysis—fast, slightly more pessimistic than a fully path-refined mode. Path-based (or path-specific) analysis can re-evaluate derates with the exact path depth/distance, recovering slack on long paths that graph mode still treats harshly. Exact mode names differ across PrimeTime-style and Tempus-style flows; the interview point is the same: AOCV is path-context-aware flat OCV, not yet a full statistical engine.

Figure 2. AOCV distance/depth table mapping to a path derate (illustrative).

Worked example B: AOCV vs flat on a long path (illustrative)#

Suppose flat late derate is (1.08) for all data stages. An AOCV table (invented) gives late (1.08) at short depth / near distance and (1.03) at long depth / far distance. A 12-stage, far path that was derated (+8\%) under flat OCV might only see (+3\%) under AOCV. On a (700\,\text{ps}) nominal data path that is roughly (56\,\text{ps}) vs (21\,\text{ps}) of extra late delay—about (35\,\text{ps}) of recovered slack before CRPR. That is why nodes migrate from flat OCV to AOCV as geometry shrinks and margins tighten.

Parametric / statistical POCV#

POCV (also discussed under names like parametric OCV, statistical OCV, or in libraries that expose LVF—Liberty Variation Format—style moments) models stage delay not as a single derated number but with mean and variation (and sometimes sensitivity to global parameters). Path slack is then computed from combined moments (or from a moment-matching / statistical timing approximation), so a long path of many stages does not pay the full short-path derate of flat OCV.

Conceptual differences:

Data table
Model What STA multiplies or combines Typical library need Pessimism tendency
Flat OCV Constant early/late factors Simple derate rules Highest on long paths
AOCV Table lookup vs depth/distance AOCV tables Medium; better on long/far paths
POCV Stage means + variances / sensitivities Variation-aware / LVF-like data Lowest blanket pessimism; needs good models

POCV is not a free lunch: you need trusted variation data, correct enablement of the analysis mode, and a clear methodology for what still belongs in clock uncertainty vs what the statistical model already covers. Do not invent foundry sigmas in an interview—explain the idea and point to the project’s sign-off kit.

Figure 3. Flat OCV vs AOCV vs POCV modelling styles (conceptual).

CRPR / CPPR: common path pessimism removal#

Early/late analysis assumes the launch clock can be fast while the capture clock is slow even on buffers that are physically the same nets. That is impossible in one silicon instance: a given buffer instance has one delay at a given moment. CRPR (Synopsys-oriented naming) / CPPR (Cadence-oriented naming) credits back the contradictory early/late difference on the common clock path from the root down to the branch point where launch and capture diverge.

Without CRPR, shared trunk buffers are late for capture and early for launch on setup—double-counted pessimism. With CRPR enabled, the tool reports a CRPR credit (or equivalent) that improves slack. Holding CRPR off during early exploration can be useful for conservatism; sign-off almost always requires the methodology’s approved CRPR/CPPR settings.

Figure 4. CRPR/CPPR common clock path credit (illustrative).

Worked example C: derates + CRPR credit (illustrative)#

Reuse example A’s nominal clock delays, but split them:

  • Common trunk (shared): (150\,\text{ps}) nominal
  • Launch-only branch: (50\,\text{ps})
  • Capture-only branch: (70\,\text{ps})
    (so launch total (200), capture total (220))

Flat early (0.95), late (1.05). Setup view without CRPR:

  • Launch clock early: entire (200 \times 0.95 = 190)
  • Capture clock late: entire (220 \times 1.05 = 231)

The common (150\,\text{ps}) was treated as both early and late. A simple CRPR-style credit for that contradiction is on the order of the early/late gap on the common segment:
(150 \times (1.05 - 0.95) = 15\,\text{ps}) of recoverable pessimism (illustrative; real tools compute credit with their own rules for min/max and reconvergence).

If example A’s OCV slack was (+288.5\,\text{ps}) before this refinement, applying a (15\,\text{ps}) CRPR credit moves slack to roughly (+303.5\,\text{ps}). On a near-zero path, that credit is often the difference between a false ECO and a clean sign-off path. Always read the report’s CRPR/CPPR line rather than hand-waving the credit in production.

Interaction with uncertainty, SI, IR and useful skew#

Derates are only one margin stack. They interact with:

  1. Clock uncertainty — jitter, margin and residual skew often still applied via set_clock_uncertainty. Stacking large uncertainty and very heavy OCV without methodology guidance double-counts. See STA in VLSI.
  2. SI / crosstalk — delta delay from coupling can be early or late depending on aggressor windows; SI-aware STA layers on top of OCV. See Crosstalk in VLSI.
  3. IR drop — voltage droop slows cells; some flows fold IR into derates or separate voltage-aware timing. See IR Drop Analysis.
  4. Temperature inversion — at low Vdd, hot can be faster; corner choice and derate polarity must match the kit. See Temperature Inversion.
  5. Useful skew — intentional clock skew helps setup or hold only if OCV/CRPR still leave positive slack after early/late on the skewed legs. See Useful Skew.
  6. CTS and ECO — clock-tree balancing and post-route ECOs change common-path length and thus CRPR credit; re-run with the same OCV mode after structural changes. See CTS and ECO.

Exceptions (set_false_path, multicycle) still apply under OCV; a false path remains false, but a real path’s slack moves with the derate mode. See Multicycle Path and False Path.

Debug flowchart: “OCV is killing my slack”#

When a path looks fine at zero derate and dies under OCV, walk a structured checklist instead of blindly upsizing cells.

Figure 5. Step-by-step flow when OCV is killing slack.

Practical report habits:

  • Confirm analysis mode: flat vs AOCV vs POCV, and graph vs path-based if applicable.
  • Check whether derates apply to clock, data, cell, net as intended.
  • Toggle or inspect CRPR/CPPR and read the credit line on the path.
  • Compare uncertainty and OCV so you are not paying twice for the same fear.
  • Isolate SI and IR by re-running with those effects off (methodology permitting) to see which knob moves slack.
  • Only then ECO: buffer, size, useful skew, or constraint fix—see ECO.

Interview Q&As#

Q1. What is OCV in STA?
A. On-chip variation modelling: STA applies early/late (or statistical) margins so launch and capture paths are not assumed to track perfectly inside one die.

Q2. Why do setup and hold use opposite early/late senses?
A. Setup fears late data and a late capture clock with an early launch clock; hold fears early data and an early capture clock with a late launch clock.

Q3. What does set_timing_derate -early/-late do?
A. It applies constant multipliers (flat OCV) to qualifying delays for min/early and max/late views. Scopes may limit clock vs data or cell vs net.

Q4. How is AOCV different from flat OCV?
A. AOCV looks up derates from tables indexed by path depth and/or distance, so long or far paths usually get smaller derates than short local paths.

Q5. Graph-based vs path-based AOCV—what is the interview sound-bite?
A. Graph-based is faster and typically more pessimistic; path-based re-evaluates derates with exact path context and can recover slack.

Q6. What is POCV at a high level?
A. A parametric/statistical model using stage variation (moments/sensitivities) so path slack reflects combined variance rather than a single worst derate.

Q7. What problem does CRPR/CPPR solve?
A. It removes illegal early-and-late pessimism on the common clock path shared by launch and capture.

Q8. Can CRPR make a real silicon failure look clean?
A. Used correctly it removes only physical impossibility. Used with wrong clock definitions or broken common-path detection it can hide issues—trust methodology and sanity checks.

Q9. Do derates replace clock uncertainty?
A. No. Uncertainty often still covers jitter and extra margin; the sign-off kit defines what each margin owns so you do not double-count.

Q10. How does useful skew interact with OCV?
A. Skew that helps at nominal may shrink or vanish after early/late on the skewed clock legs; always close useful-skew paths under the sign-off OCV mode.

Q11. Hold fails only after enabling OCV—what do you check first?
A. Early data / late launch clock derates, CRPR on the hold view, whether min-corner libraries and derates match, and accidental max derates on a hold path.

Q12. Flat → AOCV → POCV migration: what changes for a PD engineer?
A. Slack usually improves on long paths; reports gain new fields (table indices or statistical terms); ECO prioritisation should use the sign-off mode, not a looser exploratory mode.

FAQ#

Do I need AOCV if flat OCV already passes?
If the methodology’s sign-off is flat OCV and slack is healthy, you may not. Many advanced nodes require AOCV or POCV for tapeout regardless.

Are AOCV table numbers public?
Usually not. Foundry/library kits are NDA. Learn the mechanism; quote only project-approved numbers at work.

Is POCV the same as full statistical STA (SSTA)?
Related family, different products and approximations. POCV/LVF-style flows are the common “statistical flavour” in many digital sign-off kits; full SSTA is a broader topic.

Should clock nets be derated?
Typically yes for OCV on clock path delays, with CRPR to avoid common-path double-counting. Exact -clock vs -data scopes follow the kit.

Does multicycle N change OCV application?
The derate machinery still applies to the path delays; the check uses the multicycle-adjusted required/arrival relationship. See multicycle and false path.

Where do recovery/removal fit?
They use the same early/late and CRPR machinery on async-control checks. See Recovery and Removal.

Summary#

  • OCV models intra-die mismatch with early/late (or statistical) margins beyond global PVT corners.
  • Flat OCV uses constant set_timing_derate factors—simple, often pessimistic on long paths.
  • AOCV indexes derates by depth/distance (graph- or path-based) to cut blanket pessimism.
  • POCV uses parametric/statistical stage variation for still tighter modelling when libraries support it.
  • CRPR/CPPR credits back illegal early/late contradiction on the shared clock trunk.
  • Stack derates consciously with uncertainty, SI, IR and useful skew; debug mode and CRPR before ECO.
  • Close timing in the sign-off variation mode your kit mandates—not in a looser exploratory setting.

Mastering derates and CRPR is as central to modern STA interviews as setup/hold itself. Use this post with the STA series links above when you next stare at a path that “only fails under OCV.”

Written by

Swasti Pujari

Associate Director, Backend Engineering at CoreIC Technologies, with 15+ years in VLSI Physical Design and backend engineering. Previously Practice Head at UST Global, leading Physical Design, STA, EMIR, DFT, and Physical Verification. Delivered 3nm, 6nm and 7nm projects for AMD, Intel, and Microchip, and published IEEE research on hybrid AI-EDA floorplanning.