Temperature Inversion in VLSI: Causes, STA Corners and Fixes

For most of the history of CMOS, one rule held: hot silicon is slow silicon. Every timing engineer learned that the setup corner is slow process, low voltage, high temperature, and the hold corner is fast process, high voltage, low temperature. At low supply voltages that rule breaks. Cell delay can go down as temperature goes up, so the slowest corner for many paths becomes the cold one. This is temperature inversion, also called inverted temperature dependence (ITD) or temperature effect inversion.

Temperature inversion is not a curiosity. It changes which corners you sign off, which paths are critical in each corner, how you fix hold, and how a multi-voltage or DVFS design behaves across its operating modes. This guide explains the device physics in plain terms, works through illustrative numbers, and then covers what it means for static timing analysis, library corners and ECO fixing. It ends with a debug flowchart, interview questions, an FAQ and a summary.

Related reading: Static Timing Analysis (STA) in VLSI, Setup and Hold Violations, and Timing Library (.lib).

Two effects that compete#

When a transistor heats up, two of its properties change at the same time, and they push delay in opposite directions.

1. Carrier mobility drops. At higher temperature the silicon lattice vibrates more and carriers scatter more often (phonon scattering). Lower mobility means less drain current for the same gate drive, so the cell gets slower.

2. Threshold voltage drops. The threshold voltage V_T of a MOSFET falls as temperature rises. A lower V_T means a larger gate overdrive (V_GS − V_T) for the same supply, so the transistor conducts more current and the cell gets faster.

Which effect wins depends on how large the overdrive is compared with V_T. A simple way to see this is the alpha-power model of saturation current:

I_D ∝ μ(T) × (V_GS − V_T(T))^α (α typically between 1 and 2) cell delay ∝ C_load × V_DD / I_D

• At high supply voltage, the overdrive is large. A drop of a few tens of millivolts in V_T changes it by only a small percentage, while the mobility loss is a fixed percentage. Mobility wins: delay increases with temperature. This is the normal behaviour.
• At low supply voltage, close to V_T, the overdrive is small. The same few tens of millivolts are now a large fraction of it, so the V_T effect dominates. Threshold voltage wins: delay decreases with temperature. This is temperature inversion.

Between the two there is a voltage where the effects roughly cancel and delay is almost insensitive to temperature. For a single transistor this is related to the zero-temperature-coefficient (ZTC) point: the gate voltage at which the I–V curves for different temperatures cross.

Below the ZTC gate voltage the hot curve carries more current; above it the cold curve does. A logic gate whose supply sits well above this point behaves normally; one whose supply sits near or below it shows inversion. Real cells mix NMOS and PMOS devices with different threshold voltages, so a cell does not have a single, clean crossover, but the trend holds.

Kumar and Kursun showed this reversal in 2006: in a 180 nm technology at its nominal supply, circuits slowed down when temperature increased, while in a predictive 45 nm technology at its nominal supply, circuit speed improved with temperature. Dasdan and Hom (Synopsys) described the consequences for sign-off timing in the same year and named the effect inverted temperature dependence. Both papers are listed in the references.

Why it matters more at advanced nodes#

Supply voltage has scaled much faster than threshold voltage. V_T cannot drop freely because leakage grows exponentially as V_T falls. The result is a smaller ratio of V_DD to V_T, which pushes nominal and especially low-voltage operation toward the region where inversion appears. Three practical consequences follow:

• Low-voltage modes are the most exposed. A design with DVFS, adaptive voltage scaling or a near-threshold mode may behave normally in its high-voltage mode and inverted in its low-voltage mode.
• High-V_T cells are more exposed than low-V_T cells. With a higher threshold, the same supply gives a smaller overdrive, so the V_T term dominates sooner. This is why HVT-heavy, leakage-optimised paths often show the strongest inversion.
• Wires do not invert. Metal resistance rises with temperature, so interconnect delay still gets worse when hot. Paths dominated by long wires can still be worst at high temperature even in a process where cells are inverted.

Worked example 1: one cell at three supply voltages (illustrative)#

All numbers here come from the toy alpha-power model above with made-up parameters: V_T = 0.35 V at 25 °C, falling by 1 mV per °C; mobility proportional to T^−1.5 (T in kelvin); α = 1.3. They show the trend only and are not data from any real process.

Normalised cell delay (25 °C = 1.00):

What the model shows:

• At 0.50 V the cell is about 1.8 times slower at −40 °C than at 125 °C. A setup check run only at 125 °C would miss the real worst case badly.
• At 0.90 V the opposite holds: the cell is about 1.5 times slower hot than cold.
• At 0.60 V delay changes by only a few percent across the whole range. In this toy model the fastest point is near 90 °C, not at either extreme. That is the uncomfortable part of ITD: near the crossover, delay versus temperature is flat and can be non-monotonic, so the minimum-delay temperature (the one that matters for hold) is not necessarily −40 °C or 125 °C.

Worked example 2: same delay at hot, different worst corner (illustrative)#

Take two paths in the same block, both timed at a low-voltage, slow-process corner with a 470 ps clock period. Assume, purely for illustration, that cell delays are 10% larger at −40 °C than at 125 °C (inverted cells) and wire delays are 20% smaller at −40 °C (lower metal resistance).

Ignoring setup time and clock effects to keep the arithmetic simple:

• Path A passes at 125 °C with +20 ps but fails at −40 °C with −10 ps.
• Path B is worst at 125 °C (+20 ps) and has a comfortable margin when cold.

Both paths look identical in a hot-only analysis. With temperature inversion, the critical path list depends on the temperature corner, and the fix for each path is different. Path A wants cell-level fixes (upsizing, a lower-V_T swap, fewer logic levels). Path B wants wire-level fixes (layer promotion, buffering, shorter routes). See Performance (Timing) for the general timing-optimisation toolbox.

What temperature inversion does to STA corners#

Classic sign-off assumed that delay moves monotonically with voltage and temperature, so two extreme corners were enough:

• Setup (max delay): slow process, low voltage, high temperature.
• Hold (min delay): fast process, high voltage, low temperature.

Dasdan and Hom point out that ITD breaks the idea of picking corners by varying voltage and temperature independently, makes the shortest paths (and therefore hold violations) harder to find, and gets worse as supply voltages fall and threshold variation grows. In practice, teams respond in a few ways:

1. Check setup at both temperature extremes. For each slow process and low-voltage corner, time at both cold and hot. Cell-dominated paths will usually be worst cold; wire-dominated paths may be worst hot.
2. Check hold at both temperature extremes too. At the fast corner, the minimum delay may occur hot rather than cold, depending on the voltage and the cells in the path. Missing the fast-hot corner is a classic way to ship a hold escape.
3. Watch for intermediate temperatures. When the operating voltage sits near the crossover, delay versus temperature is flat and may not be monotonic. Follow the foundry and library provider's corner recommendations; some flows add an intermediate temperature corner when guidance or characterisation data shows the extremes are not bounding.
4. Analyse each voltage mode separately. A DVFS design is effectively several designs. The high-voltage mode can be hot-critical while the low-voltage mode is cold-critical, and they share one netlist and one clock tree.
5. Use libraries characterised at each temperature. Do not derive a cold corner from a hot library with linear scaling factors or a flat derate. ITD is non-linear, and a scaled library can point in the wrong direction. Use the characterised .lib for each process, voltage and temperature point and check the operating conditions in each library match the corner you think you are running.
6. Run multi-corner multi-mode (MCMM) optimisation with all relevant corners active. Fixing a path in one corner can break it in another, especially when you swap V_T flavours, which changes the cell's temperature sensitivity.

The corner names in the figure are generic and illustrative. Your exact list of process, voltage, temperature and RC extraction corners comes from the foundry, the library vendor and your product's operating specification.

What about the clock tree?#

Clock trees are built from buffers and inverters and long wires. Their insertion delay shifts with temperature, and different branches can shift by different amounts if one branch is wire-heavy and another is buffer-heavy. That changes skew between corners, which affects both setup and hold. Build the tree so that branches have a similar mix of cells and wire, check skew in every corner, and remember that CRPR only removes pessimism on the common part of the tree. See Clock Tree Synthesis (CTS) and Useful Skew.

Power and leakage are still worst hot#

Temperature inversion is about delay. Leakage still rises steeply with temperature, and electromigration limits tighten when hot. So the power and reliability sign-off corner is still high temperature even when the timing corner is cold. Do not let an inverted timing corner pull your leakage or IR-drop analysis to the wrong temperature. See Power in VLSI.

Fixing timing in an inverted corner#

The fixes are familiar; what changes is which corner you judge them in.

• Setup failing cold on a cell-dominated path: upsize drivers, reduce logic depth, or swap HVT to SVT or LVT on the worst stages. A lower-V_T cell has more overdrive, so it is both faster and less temperature-sensitive. Watch the leakage cost, which you must check at the hot corner.
• Setup failing hot on a wire-dominated path: promote the route to thicker upper metal, add or move repeaters, or shorten the route through placement.
• Hold failing in a fast-hot corner: insert delay cells or downsize near the capture flop, as usual, but verify the fix at fast-cold and at every slow corner, because the added delay is also temperature-sensitive.
• A fix in one corner breaks another: this is the normal case with ITD. Run the ECO with all sign-off corners active, not one at a time.
• Many paths marginal in both cold and hot: consider whether the low-voltage mode's voltage target is realistic. A small increase in the low-mode voltage moves the design away from strong inversion, at the cost of power. That is an architecture decision, not an ECO.

Debugging flow#

1. Confirm the corner. Check which process, voltage, temperature and RC corner the failing path comes from and that the library loaded for that corner has the operating conditions you expect.
2. Fails only cold? That is expected for cell-dominated paths at low voltage. Treat the cold corner as a real setup corner and fix the path there.
3. Is the path cell-dominated or wire-dominated? Look at the split of cell and net delay in the report. Use cell-level fixes for cell-dominated paths and wire-level fixes for wire-dominated ones.
4. Hold fails at fast-hot? Fix with delay cells and re-check at fast-cold and the slow corners.
5. Did the fix break another corner? Re-run the ECO with all MCMM corners active.
6. Re-run full sign-off across every process, voltage, temperature and RC corner in the sign-off plan.

Interview questions and answers#

Q1. What is temperature inversion? At low supply voltage, cell delay decreases as temperature increases, the opposite of the classic behaviour. It happens because the threshold-voltage drop with temperature outweighs the mobility loss when the gate overdrive is small.

Q2. Which two effects compete? Mobility falls with temperature, which slows the cell. Threshold voltage also falls with temperature, which increases overdrive and speeds the cell up. At high overdrive mobility dominates; at low overdrive V_T dominates.

Q3. What is the ZTC point? The zero-temperature-coefficient point is the gate voltage at which a transistor's drain current is roughly independent of temperature. Below it, current increases with temperature; above it, current decreases.

Q4. Are HVT or LVT cells more affected? HVT cells. A higher threshold leaves less overdrive at a given supply, so the V_T change has a larger relative effect.

Q5. Does interconnect delay show inversion? No. Metal resistance increases with temperature, so wire delay still gets worse when hot. Wire-dominated paths can be worst hot even when cell-dominated paths are worst cold.

Q6. How does temperature inversion change sign-off corners? You can no longer assume hot is the setup corner and cold is the hold corner. Setup and hold are checked at both temperature extremes for the relevant process and voltage corners, and sometimes at an intermediate temperature if the delay curve is not monotonic.

Q7. Why is hold harder to sign off with ITD? Because the temperature that gives minimum delay is no longer obviously the cold extreme. At fast process and high voltage, some paths are fastest hot. Dasdan and Hom note that ITD makes the shortest paths harder to find.

Q8. Is the leakage sign-off corner also cold under ITD? No. Leakage increases strongly with temperature, so the power corner stays hot even when the timing corner is cold.

Q9. How does DVFS interact with ITD? Each voltage mode can have a different worst temperature. The high-voltage mode may be hot-critical and the low-voltage mode cold-critical, so each mode needs its own corner set in MCMM analysis.

FAQ#

Is temperature inversion only a problem below a certain node? It depends on the supply voltage relative to the threshold voltage, not on the node name. Older nodes can show it at very low supply; newer nodes can show it at their nominal supply. Kumar and Kursun's 2006 study already showed the reversal at nominal supply in a predictive 45 nm technology.

Can I just add a margin instead of extra corners? A flat margin hides the problem but does not fix it: it penalises paths that are not temperature-critical and can still miss paths whose worst corner you never ran. Running the right corners is more reliable.

Does temperature inversion mean the chip runs faster when hot? Only for the cell-dominated part of the delay, and only in the voltage range where inversion applies. Wire delay, leakage and reliability still get worse when hot.

Do I need new libraries for ITD? You need libraries characterised at the temperatures in your sign-off plan. Most foundry and library offerings for low-voltage processes already include cold and hot variants for each voltage; check which ones your corner plan needs.

Does on-chip temperature variation matter? Yes. Different parts of a die can run at different temperatures. Sign-off typically covers the full specified junction temperature range, so every region is covered by the extremes, but check how your flow handles any on-chip variation margin for temperature.

Summary#

• Temperature changes both mobility and threshold voltage. Mobility loss slows cells; V_T drop speeds them up.
• At high supply, mobility wins and delay rises with temperature. At low supply, V_T wins and delay falls with temperature: temperature inversion.
• HVT cells and low-voltage modes are the most affected. Wires do not invert.
• Near the crossover voltage, delay is flat and can be non-monotonic in temperature.
• Sign off setup and hold at both temperature extremes for the relevant corners, analyse each voltage mode separately, and use libraries characterised at each temperature.
• Fix cell-dominated cold failures with cell-level changes and wire-dominated hot failures with wire-level changes, and always re-check every corner after an ECO.
• Leakage and reliability sign-off stay at high temperature.

References#

• A. Dasdan and I. Hom, "Handling inverted temperature dependence in static timing analysis," ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 2, pp. 306–324, April 2006: https://doi.org/10.1145/1142155.1142158
• R. Kumar and V. Kursun, "Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 10, pp. 1078–1082, October 2006: https://doi.org/10.1109/TCSII.2006.882218