Power Planning in VLSI: Rings, Stripes, Rails and PDN Design

Every standard cell, macro and I/O on a chip needs a low-resistance path to VDD and VSS. Power planning is the floorplan-stage step that builds that path: the rings, stripes (straps), follow-pin rails and via stacks that together form the power distribution network (PDN), also called the power grid or PG mesh. Get it wrong and you find out after routing, when every fix is expensive.

This guide explains power planning from a physical design point of view: the structure of a PDN, how to choose layers, widths and pitch, how macros and multiple voltage domains are hooked up, how to estimate strap drop by hand, which checks to run, and how to debug a weak grid. All numbers in the worked examples are illustrative, chosen to show the method, not taken from any foundry, library or project. Real widths, pitches, sheet resistances and EM limits come from your technology files and PDK documentation. Command snippets are simplified sketches, not complete scripts. Related reading on iVLSI: Floorplan, IR Drop Analysis in VLSI, Electromigration (EM) in VLSI, Physical-Only Cells in VLSI and Metal Layers.

What power planning has to achieve#

A power plan is a set of trade-offs between four goals:

• Low IR drop. The voltage that reaches each cell's power pins must stay within the budget set for timing sign-off. Every ohm between the supply source and the cell turns current into lost voltage.
• EM-safe current density. Each strap, rail and via must carry its average current without exceeding the electromigration limits for that layer, width and temperature.
• Enough routing resources left for signals. Every track used for power is a track signals cannot use. An over-built grid causes routing congestion; an under-built one causes IR and EM failures.
• Clean, rule-correct, connected structure. The grid must pass DRC, connect every PG pin, and align with the standard cell rows, sites and routing tracks so it does not block pin access.

Power planning happens after macro placement and before standard cell placement, because the grid shapes where cells go and how many tracks remain.

Anatomy of a power distribution network#

From the outside in, a typical frontside PDN for a block or chip has these pieces:

Straps on adjacent layers usually run in each layer's preferred routing direction, so the grid alternates horizontal and vertical from layer to layer. VDD and VSS straps are interleaved in pairs. Where a VDD strap crosses a VDD strap on the next layer, a via array connects them; where it crosses a VSS strap, nothing connects.

Follow-pin rails. Standard cells are designed with a VDD rail on one edge and a VSS rail on the other. Alternate rows are flipped so that adjacent rows share a rail: row 1 has VSS at the bottom and VDD at the top, row 2 starts with that same VDD and ends with VSS, and so on. The tool then draws a continuous rail along each row boundary, and vias drop from the lowest strap layer onto the rails wherever the straps cross them. Rails are thin and resistive, so the distance between those feed points matters a lot, as worked example B shows.

Inputs you need before you start#

• Power estimate. Average and peak power for the block, ideally split by region (for example a hot datapath versus a quiet control area).
• IR drop budget. A target such as a percentage of nominal VDD for static and dynamic drop, agreed with the timing team.
• Technology data. Sheet resistance or resistance per unit length per layer, via resistance, minimum and maximum widths, wide-metal spacing rules, and EM limits per layer and temperature.
• Package and supply topology. Wire-bond pads on the periphery or a flip-chip bump array; for a block, the PG pins or straps the top level will provide.
• Floorplan. Die and core size, row orientation, macro locations, voltage areas and any power-switch requirements from the UPF.

Choosing layers, widths and pitch#

These are the three main knobs, and they all trade IR/EM against routing.

Layers. The thick upper metals have low resistance and carry the bulk current. Intermediate layers connect that mesh down to the rails. A common pattern is: rails on the lowest metal, a fine-pitch strap layer just above it (often vertical, crossing the horizontal rails), one or two middle layers at coarser pitch, and a heavy mesh on the top two layers. Skipping layers saves tracks but forces tall via stacks that add resistance and block tracks on every layer they cross.

Width. Resistance of a strap is roughly sheet resistance × length / width, so doubling the width halves the resistance. But wider wires often trigger larger "wide metal" spacing rules, and very wide shapes may need slotting. Several narrower straps sometimes give the same resistance with fewer rule penalties.

Pitch. Halving the pitch doubles the number of straps, so each carries half the current. Pitch also sets how far current must travel along the weaker layer underneath. A tighter pitch on a lower layer helps the rails; a tighter pitch on top helps the bulk distribution.

A useful mental model is metal utilisation per layer: the fraction of a layer taken by VDD plus VSS, reviewed alongside congestion maps. The right value depends on the technology, power density and routing demand.

Alignment. Strap offsets and pitches should be multiples of the routing track pitch and consistent with the cell site width, so straps sit on tracks instead of blocking two half-tracks. At advanced nodes, the lowest strap layer must also be placed so it does not cover cell pin-access points; tools and PDKs usually provide rules for this. See Pitch, Spacing and Offset and Vias in VLSI.

Worked example A: sizing top-layer straps (illustrative)#

Suppose a 1 mm × 1 mm block draws 0.5 A average from VDD. Vertical VDD straps on the top layer run the full height, fed at both ends by a ring or by the top-level grid. Assume the current is drawn evenly along each strap.

For a wire fed at both ends with uniformly distributed load current, the worst drop is at the middle and equals:

V_max = I_strap × R_strap / 8

where I_strap is the total current drawn along that strap and R_strap is its end-to-end resistance.

Assume an illustrative sheet resistance of 0.02 Ω/sq for the thick top metal.

Option 1: 2 µm wide straps at 50 µm pitch (20 VDD straps). R_strap = 0.02 × 1000 / 2 = 10 Ω. I_strap = 0.5 / 20 = 25 mA. V_max = 0.025 × 10 / 8 ≈ 31 mV.

Option 2: 4 µm wide straps at 25 µm pitch (40 VDD straps). R_strap = 0.02 × 1000 / 4 = 5 Ω. I_strap = 0.5 / 40 = 12.5 mA. V_max = 0.0125 × 5 / 8 ≈ 7.8 mV.

Doubling both width and strap count cut the top-layer drop by four, but the VDD straps now take 4/25 = 16% of the layer, and VSS straps take the same again, so about 32% of that layer is power. Whether that is acceptable depends on how many signal routes need the top layer.

This hand calculation ignores the lower layers, the vias, the ring, the package and the VSS side (which drops too; the cell sees VDD drop plus VSS bounce). It is only a first-order check that the top mesh is in the right range before you run real rail analysis. Also check EM: each end of a strap supplies about half its current, so compare roughly 6.25 mA per 4 µm strap end against the foundry's average-current limit for that layer at the sign-off temperature.

Worked example B: rail span between feed points (illustrative)#

Follow-pin rails are much more resistive than top straps. Assume a rail resistance of 1 Ω/µm and a hot region where the cells draw 10 µA per µm of row. Vias from the strap layer above feed the rail every L µm.

Using the same formula per unit length, V_max = i × r × L² / 8:

• L = 60 µm: 10 µA/µm × 1 Ω/µm × 3600 µm² / 8 = 4.5 mV
• L = 30 µm: 10 µA/µm × 1 Ω/µm × 900 µm² / 8 ≈ 1.1 mV

Rail drop grows with the square of the feed spacing, so halving the pitch of the first strap layer cuts the rail drop by four. That is why the lowest strap layer is usually the finest pitch, and why some flows add extra short "staple" connections or a second rail layer in high-density regions.

Macros and hard IP#

Macros arrive with their own PG pins, usually on one or two specific layers as defined in their LEF. Power planning must:

• Connect every macro PG pin to the grid with enough straps and vias for its current. Memories can have several power pins (for example separate core and periphery supplies); each must reach the correct net.
• Respect the macro's routing obstructions. The grid over a macro is often limited to layers above the macro's blocked layers; lower straps are cut at the macro boundary or its halo.
• Avoid starving cells next to macros. When straps stop at a macro edge, the cells in the channel between macros may be fed only from one side. Adding straps in channels or a local ring around the macro often helps.
• Keep follow-pin rails out of macro areas and terminate them cleanly at the row ends, where endcap cells sit.

Macro placement and power planning feed each other; see Macro Placement Guidelines.

Multiple voltage domains and power gating#

A multi-voltage design needs a grid per supply:

• Separate VDD grids per voltage area, usually sharing a common VSS grid. Each voltage area has its own rails and straps for its supply, and straps of one domain stop at the boundary of another.
• Switched supplies. In a power-gated domain, the always-on supply comes in on the grid and power switch cells create the switched VDD that feeds the rails. The switch cells are placed in rows or columns within the grid. See Power Gating in VLSI.
• Secondary power pins. Retention registers, always-on buffers, isolation cells and some level shifters have a secondary supply pin. These need dedicated secondary PG routing from the always-on grid, which must be planned so it does not run out of tracks.

The UPF describes which nets exist and which cells connect to which supply. The power plan has to implement exactly that, and the connectivity check at the end must match it.

How tools build the grid#

Every implementation tool follows the same idea: declare the global nets and which pins they connect to, then describe the ring, strap and rail patterns, then let the tool create shapes and vias.

In the open-source OpenROAD flow, the PDN generator pdngen follows this pattern. A simplified sketch, adapted from the style of its documentation (layer names, widths and pitches are placeholders):

add_global_connection -net VDD -pin_pattern {^VDD$} -power add_global_connection -net VSS -pin_pattern {^VSS$} -ground set_voltage_domain -power VDD -ground VSS define_pdn_grid -name core_grid add_pdn_ring -grid core_grid -layers {metal8 metal9} -widths 5.0 -spacings 2.0 -core_offsets 4.5 add_pdn_stripe -grid core_grid -layer metal1 -followpins add_pdn_stripe -grid core_grid -layer metal4 -width 0.48 -pitch 56.0 -offset 2.0 add_pdn_stripe -grid core_grid -layer metal8 -width 1.40 -pitch 40.0 -offset 2.0 add_pdn_connect -grid core_grid -layers {metal1 metal4} add_pdn_connect -grid core_grid -layers {metal4 metal8} pdngen

Commercial tools (Cadence Innovus, Synopsys IC Compiler II) use their own commands for the same steps; the concepts carry over, the syntax does not.

Sign-off checks for the power grid#

Run a quick rail analysis right after the grid is built with estimated power, before placement. Fixing the grid then is cheap. After routing, every added strap displaces signal routes. See IR Drop Analysis in VLSI and Electromigration (EM) in VLSI for the analysis side.

Debug flowchart: IR, EM or connectivity failures in the grid#

1. Connectivity first. Floating instances or unconnected PG pins make IR results meaningless. Fix these before anything else.
2. Local or global? If the whole block is high, the top mesh, ring, bumps or package model is weak. If drop is concentrated in spots, look locally.
3. Via bottleneck? Check the resistance or current through via stacks under the hotspot. Missing or under-sized via arrays are a common and cheap fix.
4. Strap width or pitch? Add straps or tighten pitch on the layer that the drop map points to (often the lowest strap layer for rail-dominated drop).
5. Macro channel or domain boundary? Add straps in channels, local rings around macros, or more switch cells in gated domains.
6. Hot cells clustered? For dynamic drop, spread high-activity cells, add decap cells, or move clock buffers apart.
7. Re-run rail analysis and EM, then confirm the extra metal did not add congestion or DRCs. Common root causes seen in reviews: a uniform grid on a non-uniform design, too few via cuts, low straps blocking pin access, ignoring the VSS side, and unfed macro channels.

Interview Q&As#

Q1. What is power planning in VLSI physical design? It is the floorplan step that creates the power distribution network: rings, straps, follow-pin rails and via stacks that carry VDD and VSS from the bumps or pads to every cell and macro, within IR drop and EM limits.

Q2. Why are power straps placed on the upper metal layers? Upper layers are thicker and wider, so they have much lower resistance per unit length. They carry the bulk current with less drop and less EM stress, and they leave the lower layers mostly for signal routing.

Q3. What decides the pitch of the lowest strap layer? Mainly the rail drop between feed points, which grows with the square of the spacing, plus pin access and routing demand. Hot regions may need a finer pitch than the rest of the block.

Q4. How do you power a memory macro? Bring straps over or next to the macro on the layers above its PG pins, drop enough vias onto every PG pin for its current, keep lower straps and rails out of its blocked area, and make sure the channels around it are also fed.

Q5. What happens if a via stack has too few cuts? Its resistance is higher, so drop increases below it, and the current density per cut rises, which can cause via EM violations even when straps pass.

FAQ#

Is power planning the same as PG grid insertion? PG grid insertion (sometimes called stripe generation) is the step that creates the shapes. Power planning includes deciding the architecture, layers, widths, pitch and checks before and after that step.

Does every block need a core ring? No. Rings are common around chips with peripheral pads and in some blocks. In many flip-chip designs and hierarchical blocks, the straps connect directly to the top-level grid or bump structure, and a ring adds little.

How does backside power delivery change this? With backside power, most of the PDN moves to the back of the wafer and frees frontside tracks for signals. The goals stay the same, but the layer stack and via structure change. See Backside Power Delivery.

Summary#

• Power planning builds the PDN: bumps or pads, ring, upper-layer mesh, intermediate straps, via stacks and follow-pin rails.
• Layers, width and pitch trade IR drop and EM against routing resources; plan metal use per layer.
• Strap drop for a wire fed at both ends with uniform load is about I × R / 8; rail drop grows with the square of the feed spacing.
• Macros need every PG pin connected, grids respecting their obstructions, and fed channels.
• Multi-voltage designs need per-domain grids, switch cells for gated domains and secondary supply routing.
• Check connectivity, PG DRC, vias, static and dynamic IR and EM, and run a first rail analysis immediately after building the grid.

For the next steps, read IR Drop Analysis in VLSI, Electromigration (EM) in VLSI and Routing Congestion in VLSI.

References#

• OpenROAD documentation, "Power Distribution Network Generator" (pdngen): openroad.readthedocs.io