Power Gating in VLSI: Switch Cells, Isolation and Retention

Power gating turns off the supply to a block of logic when it isn't needed, so the block stops leaking. It is the main way modern SoCs cut standby power. It also adds a lot of physical design work: switch cells that must be sized and placed, a rush current that must be controlled at wake-up, isolation cells that keep floating outputs from corrupting the rest of the chip, retention registers that remember state, and always-on routing that has to survive when everything around it is off.

This guide walks through each of those pieces from a physical design and sign-off point of view. It includes worked examples (all numbers are illustrative, not from any specific library or foundry), a UPF sketch, a debug flowchart, interview Q&As and a FAQ. Related reading on iVLSI: Power in VLSI Physical Design, Unified Power Format (UPF), IR Drop Analysis in VLSI, Clock Gating and ICG, Physical-Only Cells in VLSI and Electromigration in VLSI.

Why power gating?#

Total power has two parts. Dynamic power is spent when nodes switch, and it scales with activity, capacitance, voltage squared and frequency. Clock gating attacks it by stopping the clock to idle registers. Leakage power is spent whenever the transistors have a supply, even if nothing toggles. Clock gating does nothing for leakage, because a clock-gated flop is still powered.

In advanced nodes leakage is a large share of total power, and it grows quickly with temperature. A phone SoC spends most of its life idle, so the leakage of blocks that are idle but powered can dominate battery drain. Power gating removes the supply from those blocks, so their leakage falls to the small leakage of the switch cells themselves.

The cost is complexity: wake-up latency, state loss, extra cells and area, an IR drop across the switches, and a new class of bugs that only appear when domains turn on and off.

Anatomy of a power-gated domain#

A switchable power domain is a region of the chip with its own virtual supply (often called VDDV or VDD_SW) that is connected to the real supply through switch cells. Around it sit several supporting structures:

• Power switch cells (header or footer) connect the virtual rail to the permanent rail when the domain is on.
• Isolation cells sit on outputs of the off domain and drive a known value (clamp) into the always-on logic while the domain is off.
• Retention registers keep selected state in a small always-powered latch so the block can resume without a full reset.
• Always-on (AON) cells inside the switchable region, such as buffers for the switch enable chain or for isolation and retention control, are powered from the permanent rail through a secondary power pin.
• Level shifters are added if the domain also runs at a different voltage from its neighbours. They are a separate topic, but they often share the boundary with isolation, and combined isolation level-shifter cells exist.
• A power management unit (PMU) or power controller in an always-on domain sequences everything: isolation, save, switch off, switch on, restore, release isolation.

Header vs footer switches#

A header switch is a PMOS transistor between the real VDD and the virtual VDD of the domain. A footer switch is an NMOS transistor between the virtual VSS and the real VSS.

Most SoC flows use headers. One reason is that the ground net usually stays common across the chip, which keeps substrate, I/O and analog interfaces simpler. Using both header and footer on the same domain is rare because the combined IR drop and area penalty is high.

Switch cells usually come in fine-grain and coarse-grain styles. Fine-grain gating puts a switch inside each cell or small group of cells, which is uncommon in standard-cell flows. Coarse-grain gating, the usual choice, uses an array of dedicated switch cells that feed a whole block through the virtual rail.

Placing switch cells: ring vs grid#

There are two common ways to arrange coarse-grain switches.

Ring (or boundary) style places the switches around the edge of the domain. It keeps the core rows clean and is convenient for hard macros or blocks with a perimeter supply. The drawback is that the virtual rail has to carry the full current from the edge to the centre, so IR drop rises toward the middle of a large domain.

Grid (or column/array) style places switch cells in columns or a staggered pattern throughout the domain, under the power straps. Each switch feeds a nearby area, so the virtual-rail distance is short and IR drop is more even. This is the usual choice for large standard-cell domains. The cost is that the switch columns consume placement area and must be kept clear of other cells.

Practical placement points:

• Put switch columns under the upper-level power straps so the real VDD reaches the switch input with a short via stack.
• Keep the switch pitch consistent with the power-grid pitch and the expected local current density.
• Leave the enable chain in mind while placing: the chain is routed switch to switch, so a sensible order (for example column by column) keeps it short.
• Check EM on the switch pins and vias. A switch carries a lot of current in a small area, especially during wake-up.

Rush current and the daisy-chained enable#

When a domain is off, its virtual rail has fallen toward ground and its internal capacitance (gate, wire and decap) is discharged. Turning every switch on at once would charge that capacitance as fast as the switches allow. The result is a large in-rush current that pulls down the real VDD and can upset neighbouring always-on logic, a problem often described as a supply glitch or ground bounce.

The usual fix is to turn switches on gradually:

• Daisy-chained enables. Each switch cell has an enable input and a buffered enable output. The enable ripples from switch to switch, so the switches turn on one after another, and the delay of the chain spreads the charging over time.
• Weak then strong (trickle then hammer). A first chain of small or weak switches charges the virtual rail slowly. When the rail is nearly up, a second chain of large switches turns on to give a low-resistance path for normal operation.
• Acknowledge signal. The end of the last chain comes back to the power controller as an acknowledge. The controller waits for it before restoring state and releasing isolation.

Worked example A: estimating rush current (illustrative)#

Assume a switchable domain has a total capacitance on the virtual rail of C = 20 nF (cell, wire and decap), and the supply is VDD = 0.75 V.

The charge needed to bring the virtual rail up is Q = C × V = 20 nF × 0.75 V = 15 nC.

If all switches turn on together and the rail rises in 10 ns, the average current is I = Q / t = 15 nC / 10 ns = 1.5 A. That is a very large step for one block and would cause a serious droop on the shared rail.

If a weak chain charges the rail over 1 µs instead, the average current falls to 15 nC / 1 µs = 15 mA, which the grid and package can usually absorb. The trade-off is that wake-up latency has grown by about a microsecond, plus the strong-chain delay.

This is why the wake-up time budget and the rush current limit are negotiated together between the architecture, the power team and physical design. Real numbers come from dynamic (vectorless or vector-based) power-up simulation with the actual switch models, not from this hand estimate.

Sizing switches: the IR drop across the switch#

When the domain is on, every switch is a small resistor in series with the supply. The total switch resistance adds a static IR drop to the normal grid drop.

Worked example B: how many switches? (illustrative)#

Assume:

• Peak domain current in functional mode: I = 400 mA
• Allowed drop across the switches: 15 mV (part of the total IR budget)
• On-resistance of one switch cell: R_on = 600 Ω

The total switch resistance must be at most R = 15 mV / 400 mA = 37.5 mΩ.

With N identical switches in parallel, R = R_on / N, so N ≥ 600 Ω / 37.5 mΩ = 16,000 switches.

In practice you also add margin for uneven current distribution (switches near hot spots carry more), for the resistance of the virtual rail between switches, and for the worst-case process and temperature corner. Too few switches cause timing loss inside the domain because every cell sees a lower supply. Too many cost area and add leakage in the off state, since every switch leaks a little.

Isolation cells#

When a domain is off, its outputs float. A floating input on an always-on gate can sit at mid-rail, which causes crowbar current and unpredictable logic values. Isolation cells drive a defined value on those signals while the source domain is off.

Key decisions:

• Clamp value. An AND-type isolation cell clamps to 0 when isolation is active. An OR-type cell clamps to 1. Some flows use a latch-based cell that holds the last value. The right choice depends on the receiver: for example an active-low reset or request should usually be clamped to its inactive level.
• Location. Isolation can sit in the source (switchable) domain, powered by an always-on secondary supply, or in the sink (always-on) domain. Placing it in the sink domain avoids routing an always-on supply into the switchable region, but every receiver needs its own isolation if the signal fans out.
• Enable timing. Isolation must be asserted before the supply goes down and released only after the supply is fully up and the outputs are valid. The isolation enable comes from the always-on controller, and its buffers inside the switchable region must be always-on cells.
• Inputs to the off domain. Signals going into an off domain usually don't need isolation for correctness, but driving a powered-off input can create sneak paths through protection structures. Many teams still clamp or gate them.

Retention registers#

Without retention, a block loses all its state at power-down and must be reset and reconfigured after wake-up. That can take a long time and needs software involvement. Retention registers keep chosen state in a small latch (often called a balloon or shadow latch) powered from the always-on supply.

A typical retention flop has a normal master-slave flop powered by the virtual rail, plus a retention latch powered by the permanent rail through a secondary power pin. A save signal copies the slave value into the latch before power-down. A restore signal copies it back after power-up. Some cells use a single control pin with defined polarity instead of separate save and restore.

Points to watch:

• Partial retention. Retaining every flop costs area and always-on leakage. Usually only control and configuration state is retained, and data paths are reset or recomputed.
• Clock and reset during save and restore. The clock is normally stopped and held at a defined level during save and restore. The library's retention timing checks cover save and restore relative to the clock and to each other.
• Secondary power routing. Every retention flop needs its always-on pin connected. That means always-on straps or a dedicated always-on rail through the switchable region.

The power-down and power-up sequence#

The controller follows a fixed order. A common sequence is:

1. Stop the clock to the domain (and finish any outstanding transactions on its interfaces).
2. Assert isolation so the outputs are clamped.
3. Save state into retention registers.
4. Assert reset if the design requires it for non-retained logic.
5. Turn switches off. The virtual rail decays.
6. Domain is off.
7. Turn switches on (weak chain, then strong chain) and wait for acknowledge.
8. Restore state from the retention latches.
9. Release reset, then release isolation.
10. Restart the clock.

Getting the order wrong is a classic functional bug: releasing isolation before the domain outputs are valid lets garbage into the always-on logic, and restoring before the rail is fully up can corrupt retained state.

A UPF sketch#

Power intent is written in UPF (IEEE 1801). The snippet below is a simplified illustration. Option names vary between UPF versions and tool support, so check your tool's documentation before using it.

# Illustrative UPF for a switchable domain PD_CPU (simplified) create_power_domain PD_TOP create_power_domain PD_CPU -elements {u_cpu} create_supply_net VDD create_supply_net VSS create_supply_net VDD_CPU_SW create_power_switch SW_CPU -domain PD_CPU \ -input_supply_port {vin VDD} \ -output_supply_port {vout VDD_CPU_SW} \ -control_port {sleep pmu/cpu_sw_en} \ -ack_port {ack pmu/cpu_sw_ack} \ -on_state {ON vin {!sleep}} set_isolation ISO_CPU -domain PD_CPU \ -applies_to outputs -clamp_value 0 \ -isolation_signal pmu/cpu_iso_en -isolation_sense high \ -location parent set_retention RET_CPU -domain PD_CPU \ -elements {u_cpu/ctrl_regs} \ -save_signal {pmu/cpu_save high} \ -restore_signal {pmu/cpu_restore high}

In implementation the tool reads this intent, inserts isolation and retention cells, places the switch array you specify, and connects secondary power pins. Static low-power checkers then compare the netlist with the UPF.

Physical design and sign-off checks#

Power gating adds a list of checks on top of the normal flow:

• Low-power static checks. Every crossing from a switchable domain to an always-on domain has the right isolation (and level shifting, if voltages differ), with the correct supply and control.
• Always-on connectivity. Every AON buffer, isolation cell and retention latch has its secondary power pin connected to the right always-on supply.
• Always-on buffering of control signals. Switch enables, isolation enables and save/restore signals that pass through a switchable region are buffered only with always-on cells.
• Switch enable chain. The chain is connected end to end, has no breaks, and its acknowledge reaches the controller. Its delay matches the wake-up budget.
• Static IR drop. Includes the switch resistance, in functional mode.
• Dynamic power-up analysis. Checks the rush current and the droop on the always-on rail while the domain wakes up.
• EM. Checks switch cells, their vias and the virtual rail at peak and wake-up currents.
• Timing. The domain is timed at its real (lower) effective supply, and the isolation and retention control paths are timed against the controller.
• Power-aware simulation. Proves that the sequence is correct and that corrupted values in an off domain don't leak through.
• LVS and DRC. Cover multiple supplies. LVS must understand virtual nets and secondary pins.

Debug flowchart: power-gated domain fails at wake-up#

Work from cheap checks to expensive ones:

1. Sequence order. Confirm in power-aware simulation that isolation, save, switch, restore and reset follow the intended order and wait for the acknowledge.
2. Isolation release timing. If garbage reaches the always-on side, isolation is probably released too early, or a crossing has no isolation at all.
3. Always-on connectivity. A retention latch or AON buffer tied to the switched rail loses state or breaks the enable chain. Run the low-power static checker and review its waivers.
4. Enable chain. A broken or reordered chain can leave switches off (high IR drop) or turn too many on at once (droop).
5. Rush current. If neighbouring always-on logic fails during wake-up, look at the dynamic droop and lengthen the weak phase or reduce the weak switch strength.
6. Steady-state IR drop. If the domain fails only under load after wake-up, add or redistribute switches and check the virtual-rail straps.

After any fix, re-run low-power checks, IR/EM, timing and power-aware simulation together.

Interview Q&As#

Q1. What is the difference between clock gating and power gating? Clock gating stops the clock to idle registers and saves dynamic power, but the logic stays powered and still leaks. Power gating removes the supply, which cuts leakage too, at the cost of wake-up latency, state loss and extra cells.

Q2. Why are header switches more common than footers? Headers keep a common ground across the chip, which simplifies substrate, I/O and analog interfaces. Footers are smaller for the same resistance because NMOS has higher drive, but a switched ground complicates the rest of the design.

Q3. What is rush current and how do you control it? It is the large current that charges the discharged virtual rail at wake-up. It is controlled by turning switches on gradually through a daisy-chained enable, often with a weak chain first and a strong chain after.

Q4. Why do switchable domains need isolation cells? Because outputs of an off domain float. Floating inputs on always-on logic can cause crowbar current and wrong logic values. Isolation clamps them to a safe value.

Q5. Where can an isolation cell be placed, and what are the trade-offs? In the source domain (needs an always-on supply routed into the switchable region) or in the sink domain (no always-on supply needed in the switched region, but one cell per receiver if the signal fans out).

Q6. What is a retention flop? A flop with an extra latch powered by the always-on supply. Save copies its value into the latch before power-down, and restore copies it back after power-up.

Q7. Why not retain every register? Retention cells are larger and their latches leak all the time. Usually only control and configuration state is retained.

Q8. Which cells inside a switchable domain must be always-on? Buffers on the switch enable chain, buffers for isolation and retention control that pass through the region, the retention latches and any isolation cells located in the source domain.

Q9. How does the switch array affect timing? The switches add series resistance, so cells in the domain see a lower effective supply and are slower. Timing must be signed off with that drop included.

Q10. What is the acknowledge signal for? It tells the power controller that the last switch in the chain is on, so the rail is up and the controller can restore state and release isolation.

FAQ#

Does power gating save dynamic power? Only while the domain is off. When it is on, the switches add a little IR drop and slightly reduce performance, so dynamic power is not reduced.

Is power gating worth it for short idle periods? Not always. Turning off and on costs energy (recharging the rail and the save/restore operations). If the idle period is shorter than the break-even time, the block should only be clock gated.

Can a domain be both power-gated and run at a different voltage? Yes. It then needs both isolation and level shifting at its boundary, often in a combined cell.

Do memories get power gated the same way? Memories usually have their own low-power modes (such as retention or periphery shutdown) controlled by pins defined by the memory compiler, so follow its datasheet rather than wrapping the macro in standard switch cells.

Where can I read more? The IEEE 1801 (UPF) standard defines the power-intent language, and the Low Power Methodology Manual by Keating, Flynn, Aitken, Gibbons and Shi (Springer, 2007) is a widely used reference on power gating, isolation and retention.

Summary#

• Power gating removes the supply from idle logic to cut leakage, which clock gating cannot touch.
• A switchable domain needs switch cells (usually PMOS headers), isolation on its outputs, optional retention registers, always-on cells for control paths and a power controller that sequences everything.
• Grid-style switch placement keeps the virtual-rail IR drop low in large domains. Ring-style suits smaller blocks and macros.
• Rush current at wake-up is controlled with a daisy-chained enable, usually weak then strong, with an acknowledge back to the controller.
• Size switches so their series resistance fits the IR drop budget, and sign off dynamic power-up droop, EM, low-power static checks and power-aware simulation.
• Most wake-up bugs come from the sequence order, early isolation release or a missing always-on connection, so check those first.