timing

ECO (Engineering Change Order) in VLSI physical design explained: timing, DRV, noise, leakage and functional ECOs, pre-mask vs post-mask (metal-only) changes, spare cells, the sign-off STA to place-and-route ECO loop, what to re-verify after every ECO and how to debug an ECO that will not converge, with illustrative examples and interview Q&As.

Multicycle paths and false paths in STA explained for physical design and timing engineers: how set_multicycle_path moves setup and hold checks, why setup N needs hold N-1, -start vs -end across clocks, valid and dangerous false paths, clock groups, exception precedence and a debugging flow, with illustrative examples and interview Q&As.

The difference between a latch and a flip-flop explained for physical design and STA engineers: level vs edge triggering, master-slave structure, where setup and hold are checked, time borrowing, phase-dependent hold, ICG and lockup latches, and unintended RTL latches, with illustrative examples, a debug flowchart and interview Q&As.

IR drop analysis in VLSI explained for physical design engineers: where supply and ground drop come from, static vs dynamic IR drop, vectorless and vector-based analysis, how IR drop affects setup and hold, and how to debug and fix hotspots, with illustrative examples, a flowchart and interview Q&As.

How time budgeting splits the timing of paths that cross block boundaries in a hierarchical design: input and output delays in block SDC, ways to divide slack, clocks, exceptions and hold budgets, and how to debug and re-budget interface violations, with illustrative examples, a flowchart and interview Q&As.

Why cell delay can fall as temperature rises at low supply voltage, how mobility and threshold voltage compete, and what temperature inversion means for STA corners, hold sign-off, DVFS modes and timing fixes.