Well Tap Cells

Latch-up in CMOS explained for physical designers: the parasitic PNPN (SCR) mechanism, triggers, holding voltage and current, tap cells and guard rings, SOI/FinFET, JEDEC JESD78 testing, layout checks and interview questions.

Tap Cell Placement: Latch-up condition: Latch-up basically means a short circuit condition between power and ground. Due to this short circuit condition, a low impedance path is created. So in order to limit this resistance between power and ground connections to wells of the substrate, Tap cells are used.