VLSI Interview Questions and Answers

ECO (Engineering Change Order) in VLSI physical design explained: timing, DRV, noise, leakage and functional ECOs, pre-mask vs post-mask (metal-only) changes, spare cells, the sign-off STA to place-and-route ECO loop, what to re-verify after every ECO and how to debug an ECO that will not converge, with illustrative examples and interview Q&As.

What is routing? Creating physical connections to all the logical connections present in the design with the help of metal layers is known as routing. What are the types of routing? What are the pre routing checks? What are the goals of routing? What are the stages of routing?

What is placement? Placing of standard cells in the design is known as placement. What are the pre placement sanity checks? What are the stages of placement? What are the objectives/quality checks of placement? What is congestion? If the number of required routing resources are more than the number of available routing tracks, then this […]

What are the inputs at the floorplan stage? What are the two types of lef and what is present in both the lef ? What is there in .lib file? The timing library is an ASCII representation of the Timing, Power and Area associated with the standard cells. What kind of physical libraries are used? […]