Creating physical connections to all the logical connections present in the design with the help of metal layers is known as routing.
What are the types of routing?
- PG Route: Power/Ground physical routing is completed during floorplan. Secondary PG routing happens just after STD cell placement.
- Clock Route: Clock physical routing is completed during CTS after clock buffer insertion.
- Signal Route: All the signal routing are completed after all the cells are placed which is called as routing stage.
What are the pre routing checks?
- All the Physical cells and Standard cells should be placed properly inside the core area.
- Clock cells should be placed and clock routing should be completed. Clock NDR should be applied for the required or all clock nets.
- Acceptable congestion, Timing (Setup/Hold), Power and Logical DRCs.
- We should fix all the assign statements where 1’b0 should be connected via TIE low and similarly 1’b1 should be connected to TIE high cell.
- ATPG and scan coverage should be proper. The entire design should have testability.
- PDN report (Low Power report) should be clean.
- Logical Equivalence should be clean.
- Max Tran, Max Cap, Max Load etc. violations should not be too high. Marginal can be handled during routing or ECO stage.
What are the goals of routing?
- Route all the signal nets with minimal physical DRCs.
- Optimize Data path logic for timing, DRCs and Power.
- Quality of route in a way, post route CTO is optionally performed.
What are the stages of routing?
- Global Routing
- Track Assignment
- Detail Routing
Written by
Swasti Pujari
Associate Director, Backend Engineering at CoreIC Technologies, with 15+ years in VLSI Physical Design and backend engineering. Previously Practice Head at UST Global, leading Physical Design, STA, EMIR, DFT, and Physical Verification. Delivered 3nm, 6nm and 7nm projects for AMD, Intel, and Microchip, and published IEEE research on hybrid AI-EDA floorplanning.
