6 articles tagged with this topic.
Routing congestion in VLSI explained for physical design engineers: how global routers measure GCell capacity, demand and overflow, cell density vs pin density, global, local and layer congestion, floorplan, logic and placement causes, fixes with halos, partial blockages and cell padding, the timing impact, a debugging flowchart and interview Q&As.
What technology DRCs check and why: width, width- and run-length-dependent spacing, end-of-line, minimum area, enclosure, cut, notch and density rules, how the tech LEF differs from the sign-off runset, and how to debug DRC violations, with illustrative examples, a flowchart and interview Q&As.
Why double patterning is needed below the single-exposure pitch limit, how LELE and SADP work, what coloring, odd-cycle conflicts and stitches mean, and how DPT changes placement, routing, extraction and DRC, with illustrative examples, a debug flowchart and interview Q&As.
Pitch The distance between the center to center of the metal is called as pitch. In the below picture, B is pitch. Spacing Spacing is the distance between the edge to edge metal layers. The distance A is spacing in below picture. Offset Offset is the distance between the core and first metal layer. In […]
Overview of Routing Types of Routes Clock physical routing is completed during CTS after clock buffer insertion. Pre-Route Checks The pre-route checks that need to be done are as follows: Goals of Routing
The physical design flow in VLSI is where your chip design starts coming to life. After the synthesis stage, it’s time to take your design from a logical blueprint to a physical layout that can actually be fabricated on silicon. This phase is intricate, involving specialized tools, precise inputs, and detailed steps to ensure everything […]
