Legalization

ECO (Engineering Change Order) in VLSI physical design explained: timing, DRV, noise, leakage and functional ECOs, pre-mask vs post-mask (metal-only) changes, spare cells, the sign-off STA to place-and-route ECO loop, what to re-verify after every ECO and how to debug an ECO that will not converge, with illustrative examples and interview Q&As.

What PODE and CPODE are, how single and double diffusion breaks differ, and what cell-edge rules mean for placement, legalization, fillers and ECOs at FinFET and GAA nodes.

Refine Placement (Legalization) There are number of tool options which we can use for refining the placement, like you can set some micron distance so that tool will not move those cells more than specified distance. Detailed Placement