Layout Verification

What technology DRCs check and why: width, width- and run-length-dependent spacing, end-of-line, minimum area, enclosure, cut, notch and density rules, how the tech LEF differs from the sign-off runset, and how to debug DRC violations, with illustrative examples, a flowchart and interview Q&As.

The physical design flow in VLSI is where your chip design starts coming to life. After the synthesis stage, it’s time to take your design from a logical blueprint to a physical layout that can actually be fabricated on silicon. This phase is intricate, involving specialized tools, precise inputs, and detailed steps to ensure everything […]