3 articles tagged with this topic.
Routing congestion in VLSI explained for physical design engineers: how global routers measure GCell capacity, demand and overflow, cell density vs pin density, global, local and layer congestion, floorplan, logic and placement causes, fixes with halos, partial blockages and cell padding, the timing impact, a debugging flowchart and interview Q&As.
Scan chain reordering in VLSI physical design explained: why synthesis scan order wastes wirelength, what the scan DEF (START/STOP, FLOATING, ORDERED, PARTITION, MAXBITS) allows, clock-domain, edge-order and lockup-latch rules, chain balancing, scan shift hold timing, verification and ATPG regeneration, with illustrative examples, a debugging flowchart and interview Q&As.
What is Placement Optimization? Depending on the stages of the design, optimization can include the following operations: Secondary PG Routing As we know there are many partitions now a days, so we are dealing with UPF and number of power domains. We use AON cells (we discussed in Floorplan section) in the gated partition to […]
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