Halo

Routing congestion in VLSI explained for physical design engineers: how global routers measure GCell capacity, demand and overflow, cell density vs pin density, global, local and layer congestion, floorplan, logic and placement causes, fixes with halos, partial blockages and cell padding, the timing impact, a debugging flowchart and interview Q&As.

What are Placement and Routing Blockages in VLSI? There are basically two types of blockages in VLSI,.i.e., Placement Blockages and Routing Blockages. The Placement Blockages are again classified into three types. They are hard blockages, soft blockages and partial blockages. These are explained in details below. Placement blockage Placement blockages are the areas where placement […]