Flip Flop

The difference between a latch and a flip-flop explained for physical design and STA engineers: level vs edge triggering, master-slave structure, where setup and hold are checked, time borrowing, phase-dependent hold, ICG and lockup latches, and unintended RTL latches, with illustrative examples, a debug flowchart and interview Q&As.

How multi-bit flip-flops save clock power, which flops can be banked, the timing and useful-skew trade-offs, and a practical method for debanking, with worked examples.