CMOS Inverter: Working, VTC, Noise Margins, Delay and Power
The CMOS inverter explained for VLSI and physical design engineers: PMOS/NMOS structure and switch model, VTC regions, switching threshold, noise margins, propagation delay and slew, dynamic, short-circuit and leakage power, standard-cell layout and latch-up, its role in CTS and STA, a timing debug flowchart and interview Q&As.